The Global Co-Packaged Optics Market 2026-2036

1             EXECUTIVE SUMMARY            35

• 1.1        Report Overview and Key Findings   35
• 1.2        Market Definition and Scope               35
  • 1.2.1    Definition of Co-Packaged Optics (CPO)     35
  • 1.2.2    Scope of This Report 36
• 1.3        Key Market Drivers and Restraints   36
• 1.4        Modern High-Performance AI Data Centre Architecture    37
  • 1.4.1    Physical Infrastructure Hierarchy     37
  • 1.4.2    Network Architecture                38
  • 1.4.3    Power and Cooling Considerations 38
• 1.5        Switches: Key Components in Modern Data Centres          39
  • 1.5.1    Switch Architecture Evolution            39
  • 1.5.2    Switch ASIC Technology         40
  • 1.5.3    Optical Transceiver Requirements   41
• 1.6        Advancements in Switch IC Bandwidth and the Need for CPO Technology          41
  • 1.6.1    Historical Bandwidth Scaling              41
  • 1.6.2    SerDes Technology Evolution              42
  • 1.6.3    Electrical Signalling Limits    42
  • 1.6.4    Front-Panel Density Constraints      42
  • 1.6.5    Power Consumption Trajectory         42
• 1.7        Overview of Key Challenges in Data Centre Architectures               43
  • 1.7.1    Thermal Management             43
  • 1.7.2    Power Delivery              43
  • 1.7.3    Cable Management   43
  • 1.7.4    Reliability and Serviceability                44
  • 1.7.5    Standards and Interoperability           44
• 1.8        Key Trend of Optical Transceivers in High-End Data Centres          44
  • 1.8.1    Historical Evolution   44
  • 1.8.2    Technology Migration Path    45
• 1.9        Design Decisions: CPO vs. Pluggables Comparison           48
  • 1.9.1    Performance Comparison    48
  • 1.9.2    Operational Comparison       48
  • 1.9.3    Economic Comparison           48
• 1.10     What is an Optical Engine (OE)?       49
  • 1.10.1 Functional Description            49
  • 1.10.2 Optical Engine Components               49
  • 1.10.3 Performance Parameters       50
• 1.11     Heterogeneous Integration and Co-Packaged Optics         50
  • 1.11.1 The Heterogeneous Integration Imperative 51
  • 1.11.2 Integration Approaches for CPO       51
  • 1.11.3 TSMC's Role in Heterogeneous Integration 52
• 1.15     Overview of Interconnection Techniques in Semiconductor Packaging 52
  • 1.15.1 Wire Bonding 53
  • 1.15.2 Flip-Chip Bumping     53
  • 1.15.3 Micro-Bumping            53
  • 1.15.4 Through-Silicon Via (TSV)       53
  • 1.15.5 Hybrid Bonding            53
  • 1.15.6 Redistribution Layer (RDL)    54
• 1.16     Key CPO Applications: Network Switch and Computing Optical I/O         54
  • 1.16.1 Scale-Out Network Switching            54
  • 1.16.2 Scale-Up Computing Optical I/O      55
• 1.17     EIC/PIC Integration by Advanced Interconnect Techniques            56
  • 1.17.1 Integration Requirements      56
• 1.18     2D to 3D EIC/PIC Integration Options            57
  • 1.18.1 2D Integration Architecture   57
  • 1.18.2 2.5D Integration Architecture              58
  • 1.18.3 3D Integration Architecture   58
• 1.19     Benchmark of Different Packaging Technologies for EIC/PIC         63
• 1.20     Examples of Packaging a 3D Optical Engine with an IC      64
  • 1.20.1 Configuration 1: EIC-on-PIC with Micro-Bumps     64
  • 1.20.2 Configuration 2: PIC-on-EIC with Through-Silicon Vias     64
  • 1.20.3 Configuration 3: 3D SoIC with Hybrid Bonding        64
• 1.21     Types of CPO + XPU/Switch ASIC Packaging Structures    65
  • 1.21.1 Type I: Optical Engines on Package Periphery          65
  • 1.21.2 Type II: Optical Engines Co-Located with ASIC on Interposer        65
  • 1.21.3 Type III: 3D Stacked Optical Engines              66
• 1.22     Challenges and Future Potential of CPO Technology           67
  • 1.22.1 Technical Challenges               67
  • 1.22.2 Commercial Challenges        67
    • 1.22.2.1            Future Potential           67
• 1.23     NVIDIA vs. Broadcom: Strategic Comparison in AI Infrastructure and CPO         68
  • 1.23.1 NVIDIA's CPO Strategy: Vertical Integration               68
  • 1.23.2 Broadcom's CPO Strategy: Open Ecosystem           69
  • 1.23.3 Competitive Dynamics           69
  • 1.23.4 CPO Product Benchmark: NVIDIA vs. Broadcom   70
  • 1.23.5 NVIDIA and Broadcom: Divergent CPO Ecosystems           70
• 1.24     Current AI System Architecture          71
  • 1.24.1 NVIDIA DGX/HGX Architecture           71
• 1.25     Future AI Architecture              71
• 1.26     Market Forecast           72
  • 1.26.1 Server Boards, CPUs, and GPUs/Accelerators         72
  • 1.26.2 Optical I/O for AI Interconnect CPO Forecast (Units Shipped)      72
  • 1.26.3 Optical I/O for AI Interconnect CPO Forecast (Revenue/Market Size)      73
  • 1.26.4 CPO Network Switches for AI Accelerators Forecast (Units Shipped)      74
  • 1.26.5 CPO Network Switches for AI Accelerators Forecast (Market Size and Revenue)             75
  • 1.26.6 Total CPO Market Overview  76
  • 1.26.7 Total CPO by Different EIC/PIC Integration Technology (Unit Shipments)              77
  • 1.26.8 System Integration of Network Switches by Packaging Technologies       78
  • 1.26.9 System Integration of Optical I/O Forecast by Packaging Technologies  79
• 1.27     Co-packaged optics (CPO) industrial ecosystem  79
  • 1.27.1 PIC Design Segment  79
  • 1.27.2 ASIC and xPU Design Segment           80
  • 1.27.3 Laser Sources Segment          82
  • 1.27.4 SOI Wafer and Epi-Wafer Segment  82
  • 1.27.5 EIC, Retimers, SerDes, and PHY Segment  83
  • 1.27.6 Connectors and Fibers Segment      84
  • 1.27.7 Foundries Segment    84
  • 1.27.8 Packaging, Assembling, and Testing Segment         85
  • 1.27.9 System and Equipment Segment     86
  • 1.27.10              End Customers (Hyperscalers) Segment    86
  • 1.27.11              Ecosystem Interdependencies and Strategic Implications              87

2             CHALLENGES AND SOLUTIONS FOR FUTURE AI SYSTEMS            90

• 2.1        The Rise and Challenges of Large Language Models (LLMs)           90
  • 2.1.1    The Explosive Growth of AI and Generative AI           90
    • 2.1.1.1 Historical Context and Acceleration               90
    • 2.1.1.2 Compute Demand Scaling   90
    • 2.1.1.3 Generative AI Market Expansion       90
  • 2.1.2    Modern High-Performance AI Data Centre Requirements               92
    • 2.1.2.1 Compute Density Requirements      92
    • 2.1.2.2 Network Topology Requirements      92
    • 2.1.2.3 Availability and Reliability Requirements    92
  • 2.1.3    NVIDIA's State-of-the-Art AI Systems             93
    • 2.1.3.1 DGX H100 and HGX H100     93
  • 2.1.4    Switches: Key Components in Modern Data Centres          95
    • 2.1.4.1 Switch Hierarchy in AI Data Centres               95
• 2.2        Scale-Up, Scale-Out, and Scale-Across Networks               96
  • 2.2.1    Scale-Up Networks: GPU-to-GPU Interconnects   96
    • 2.2.1.1 NVIDIA NVLink Implementation        96
    • 2.2.1.2 CPO Value Proposition for Scale-Up               97
  • 2.2.2    Scale-Out Networks: Rack-to-Rack Communications      98
    • 2.2.2.1 Ethernet-Based Scale-Out    98
    • 2.2.2.2 InfiniBand for AI            98
    • 2.2.2.3 CPO Value Proposition for Scale-Out            98
  • 2.2.3    Scale-Up, Scale-Out, and Scale-Across Comparison        99
• 2.3        Challenges in Network Switch Interconnects for High-End Data Centres              100
  • 2.3.1    Roadmap of Interconnect Technology for Network Switches in High-End Data Centres              100
    • 2.3.1.1 Technology Generations         100
  • 2.3.2    SerDes Bottleneck in High-Bandwidth Systems     102
    • 2.3.2.1 SerDes Function          102
    • 2.3.2.2 Channel Loss Challenges      102
  • 2.3.3    Solutions to SerDes Bottlenecks in High-Bandwidth Systems      103
    • 2.3.3.1 Linear-Drive Electronics         103
    • 2.3.3.2 Near-Package Optics                103
    • 2.3.3.3 Co-Packaged Optics 103
  • 2.3.4    Pluggable Optics: Current Bottlenecks and Limitations   104
    • 2.3.4.1 Form Factor Constraints        104
    • 2.3.4.2 Electrical Interface Limitations          104
    • 2.3.4.3 Thermal Management Challenges   104
    • 2.3.4.4 Serviceability Trade-offs        104
  • 2.3.5    On-Board Optics (OBO)          105
  • 2.3.6    Co-Packaged Optics (CPO)  106
    • 2.3.6.1 CPO Architecture        106
    • 2.3.6.2 Key Enabling Technologies    107
    • 2.3.6.3 Performance Benefits              107
    • 2.3.6.4 Implementation Challenges 107
  • 2.3.7    Transmission Losses in Pluggable Optical Transceiver Connections        108
    • 2.3.7.1 Total Path Loss             108
  • 2.3.8    Pluggable Optics vs. CPO      109
  • 2.3.9    Design Decisions for CPO Compared to Pluggables           110
  • 2.3.10 Advancements in Switch IC Bandwidth and the Need for CPO Technology          111
    • 2.3.10.1            Bandwidth Scaling Trajectory              111
    • 2.3.10.2            Physical Constraints at Scale              111
  • 2.3.11 L2 Frontside Network Architecture Diagram: CPO vs. Non-CPO 112
• 2.4        Challenges in Compute Switch Interconnects (Optical I/O) for High-End Data Centres              113
  • 2.4.1    Number of Copper Wires in Current AI System Interconnects       113
    • 2.4.1.1 NVLink Copper Cable Count               113
    • 2.4.1.2 SuperPOD Cable Complexity              113
  • 2.4.2    Limitations of Current Copper Systems in AI            114
  • 2.4.3    NVIDIA's Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems          115
    • 2.4.3.1 Current Generation: Copper-Centric             116
    • 2.4.3.2 Transition Generation: Hybrid Approach     116
    • 2.4.3.3 Future Generation: Optical-First       116
    • 2.4.3.4 Strategic Implications              116
  • 2.4.4    Copper vs. Optical for High-Bandwidth Systems: Benchmark      116
  • 2.4.5    Migration from Copper to Optical Interconnects for High-End AI Systems            117
  • 2.4.6    Current AI System Architecture          118
  • 2.4.7    L1 Backside Compute Architecture with Copper Systems              119
  • 2.4.8    L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO)    120
  • 2.4.9    Opportunities for Swapping Copper to Optical       120
• 2.5        Future AI Systems in High-End Data Centres            121
  • 2.5.1    Power Efficiency Comparison: CPO vs. Pluggable Optics vs. Copper Interconnects      121
    • 2.5.1.1 Power Consumption Breakdown      121
  • 2.5.2    Latency of 60cm Data Transmission Technology Benchmark        123
  • 2.5.3    Future AI Architecture (Short to Mid-Term) 123
  • 2.5.4    Future AI Architecture (Long-Term)  125

3             INTRODUCTION TO CO-PACKAGED OPTICS (CPO)             128

• 3.1        Photonic Integrated Circuits (PICs) Key Concepts 128
  • 3.1.1    What are Photonic Integrated Circuits (PICs)?         128
    • 3.1.1.1 Fundamental Definition         128
    • 3.1.1.2 Material Platforms      128
    • 3.1.1.3 Integration Levels        128
  • 3.1.2    PICs vs. Silicon Photonics: What are the Differences?       130
    • 3.1.2.1 Silicon Photonics: A Specific Implementation         130
    • 3.1.2.2 Why Silicon Photonics Dominates CPO       130
  • 3.1.3    PIC Architecture           131
    • 3.1.3.1 Transmit Path Architecture    131
    • 3.1.3.2 Receive Path Architecture     132
    • 3.1.3.3 Supporting Functions               132
  • 3.1.4    Advantages and Challenges of PICs               133
• 3.2        Optical Engine (OE)   134
  • 3.2.1    What is an Optical Engine?   134
    • 3.2.1.1 Optical Engine Composition               134
    • 3.2.1.2 Optical Engine vs. Pluggable Transceiver    135
  • 3.2.2    How an Optical Engine Works            135
    • 3.2.2.1 Transmit Path Operation         135
    • 3.2.2.2 Receive Path Operation          136
    • 3.2.2.3 Critical Performance Parameters     136
  • 3.2.3    Optical Power Supplies           136
    • 3.2.3.1 Why External Laser Sources?              136
    • 3.2.3.2 External Laser Source Architectures              137
    • 3.2.3.3 Optical Power Delivery            137
• 3.3        Co-Packaged Optics 138
  • 3.3.1    Three Key Concepts in Co-Packaged Optics (CPO)              138
    • 3.3.1.1 Concept 1: Proximity Integration       138
    • 3.3.1.2 Concept 2: Functional Partitioning 138
    • 3.3.1.3 Concept 3: Coherent Ecosystem Development      138
  • 3.3.2    Key Technology Building Blocks for CPO      139
    • 3.3.2.1 Silicon Photonics PIC               139
    • 3.3.2.2 Electronic IC (EIC)      140
    • 3.3.2.3 EIC-PIC Integration    140
    • 3.3.2.4 Fibre Array Units (FAUs)          140
    • 3.3.2.5 External Laser Source              140
    • 3.3.2.6 Advanced Packaging Platform            140
  • 3.3.3    Benefits of CPO: Latency Reduction              142
    • 3.3.3.1 Sources of Latency in Optical Interconnects            142
    • 3.3.3.2 CPO Latency Advantages      142
  • 3.3.4    Benefits of CPO: Power Consumption Reduction  143
    • 3.3.4.1 Power Consumption Breakdown      143
    • 3.3.4.2 Why CPO Consumes Less Power     144
  • 3.3.5    Benefits of CPO: Data Rate Improvements 144
    • 3.3.5.1 Pluggable Scaling Limitations             144
    • 3.3.5.2 CPO Scaling Advantages       145
    • 3.3.5.3 Data Rate Scaling Roadmap               145
  • 3.3.6    Overview of Value Proposition of CPO          145
    • 3.3.6.1 Value for Hyperscale Data Centre Operators            145
    • 3.3.6.2 Value for Network Equipment Vendors         146
    • 3.3.6.3 Value for the Technology Ecosystem              146
  • 3.3.7    Future Challenges in CPO     146
    • 3.3.7.1 Manufacturing and Yield Challenges             146
    • 3.3.7.2 Thermal Management Challenges   146
    • 3.3.7.3 Serviceability and Reliability Challenges    147
    • 3.3.7.4 Ecosystem and Standardisation Challenges            147
    • 3.3.7.5 Cost Challenges          147
• 3.4        CPO Standards            148
  • 3.4.1    OIF Co-Packaging Framework            148
  • 3.4.2    OIF Standards for 1.6T and 3.2T CPO Module          149
  • 3.4.3    External Laser Small Form Pluggable (ELSFP) Implementation Agreement          150
  • 3.4.4    Telemetry and Management 150
  • 3.4.5    OIF's CEI-112G XSR / XSR+ PAM4     151
  • 3.4.6    UCIe Standard and Its Relationship to CPO              151
  • 3.4.7    The CPO Standards Process in China           152

4             PACKAGING FOR CO-PACKAGED OPTICS (CPO)  154

• 4.1        Introduction to CPO Packaging         154
  • 4.1.1    Key Components to be Packaged in an Optical Transceiver           154
    • 4.1.1.1 Photonic Integrated Circuit (PIC)      154
    • 4.1.1.2 Electronic Integrated Circuit (EIC)   154
    • 4.1.1.3 Laser Source Interface            154
    • 4.1.1.4 Fibre Array Unit (FAU)               154
    • 4.1.1.5 Host ASIC Interface   155
  • 4.1.2    Heterogeneous Integration and Co-Packaged Photonics 155
    • 4.1.2.1 Why Heterogeneous Integration for CPO?  155
    • 4.1.2.2 Heterogeneous Integration Approaches for CPO   156
    • 4.1.2.3 Integration Hierarchy for CPO             156
  • 4.1.3    CPO for Network Switch: Packaging Concept          156
    • 4.1.3.1 Switch Architecture with CPO            156
    • 4.1.3.2 Package Configuration Options         157
    • 4.1.3.3 Packaging Requirements for Switch CPO    157
  • 4.1.4    1.6 Tbps Co-Packaged Optics for Network Switch                157
    • 4.1.4.1 Integration Approach                158
  • 4.1.5    CPO as Optical I/O for XPUs: Packaging Concept 159
    • 4.1.5.1 The Scale-Up Interconnect Challenge          159
    • 4.1.5.2 XPU-CPO Packaging Concept             159
    • 4.1.5.3 Implementation Approaches              159
    • 4.1.5.4 NVIDIA's Approach to XPU Optical I/O          163
    • 4.1.5.5 Packaging Implications for XPU Optical I/O               163
    • 4.1.5.6 System Architecture Evolution           163
  • 4.1.6    CPO Integration for Compute Silicon             164
    • 4.1.6.1 System Configuration              164
    • 4.1.6.2 Integration Architecture          165
    • 4.1.6.3 Thermal Partitioning 165
    • 4.1.6.4 Enabled Architectures             165
  • 4.1.7    Overview of CPO Packaging Technologies  165
• 4.2        Overview and Development Roadmap of 2.5D and 3D Advanced Semiconductor Packaging Technologies  167
  • 4.2.1    Evolution Roadmap of Semiconductor Packaging 167
  • 4.2.2    Semiconductor Packaging Overview             168
  • 4.2.3    Key Metrics for Advanced Semiconductor Packaging Performance          171
  • 4.2.4    Overview of Interconnection Techniques in Semiconductor Packaging 175
  • 4.2.5    Overview of 2.5D Packaging Structure          178
  • 4.2.6    2.5D Package Components 178
  • 4.2.7    Benefits for CPO          178
  • 4.2.8    Challenges for CPO   178
• 4.3        2.5D Silicon-Based Packaging Technologies            179
  • 4.3.1    2.5D Packaging Involving Silicon as Interconnect  179
  • 4.3.2    Silicon Interposer Technology             179
  • 4.3.3    Silicon Bridge Technology      179
  • 4.3.4    CPO Implications        180
  • 4.3.5    Through-Silicon Via (TSV): Current State and Future            184
    • 4.3.5.1 TSV Fabrication Process         184
    • 4.3.5.2 TSV Technology Generations               185
    • 4.3.5.3 TSV Challenges for CPO         185
    • 4.3.5.4 Future TSV Development        186
  • 4.3.6    Development Trends for 2.5D Silicon-Based Packaging   188
    • 4.3.6.1 Interposer Size Scaling            188
    • 4.3.6.2 Routing Density Advancement           188
    • 4.3.6.3 Cost Reduction Initiatives     188
    • 4.3.6.4 Integration with Advanced Features                188
  • 4.3.7    Silicon Interposer vs. Silicon Bridge Benchmark    192
    • 4.3.7.1 Implications for CPO 193
• 4.4        2.5D Organic-Based Packaging Technologies          194
  • 4.4.1    2.5D Packaging: High-Density Fan-Out (FO) Packaging    194
    • 4.4.1.1 Fan-Out Technology Concept             194
    • 4.4.1.2 High-Density Fan-Out Variants          194
    • 4.4.1.3 Advantages for CPO  194
    • 4.4.1.4 Challenges for CPO   194
  • 4.4.2    Redistribution Layer (RDL)    194
    • 4.4.2.1 RDL Fabrication Process        194
    • 4.4.2.2 RDL Design Considerations for CPO              195
  • 4.4.3    Electronic Interconnects: SiO2 vs. Organic Dielectric         196
  • 4.4.4    Panel Level Fab-Out  198
    • 4.4.4.1 Panel-Level Processing           198
    • 4.4.4.2 Advantages for CPO  198
    • 4.4.4.3 Challenges for CPO   198
  • 4.4.5    Wafer Level Fan-Out 199
    • 4.4.5.1 Wafer-Level Processing          199
    • 4.4.5.2 Advantages for WLFO               199
    • 4.4.5.3 Challenges for WLFO                200
  • 4.4.6    Wafer-Level Fan-Out vs. Panel-Level Fan-Out         200
    • 4.4.6.1 Selection Criteria for CPO     201
  • 4.4.7    Key Trends in Fan-Out Packaging     201
  • 4.4.8    Challenges in Future Fan-Out Processes    203
    • 4.4.8.1 Die Shift and Placement Accuracy   203
    • 4.4.8.2 Warpage Control         203
    • 4.4.8.3 Yield and Cost               203
    • 4.4.8.4 High-Frequency Performance             204
• 4.5        2.5D Glass-Based Packaging Technologies               206
  • 4.5.1    Roles of Glass in Semiconductor Packaging            206
    • 4.5.1.1 Glass Properties Relevant to Packaging      206
    • 4.5.1.2 Applications in Packaging     207
    • 4.5.1.3 Glass Core as Interposer for Advanced Semiconductor Packaging          208
  • 4.5.2    Overcoming Limitations of Silicon Interposers with Glass              210
    • 4.5.2.1 Size Limitation              210
    • 4.5.2.2 Optical Opacity            210
    • 4.5.2.3 Dielectric Loss              210
    • 4.5.2.4 Cost Structure               210
    • 4.5.2.5 Remaining Silicon Advantages           210
  • 4.5.3    Glass vs. Molding Compound             211
    • 4.5.3.1 Implications for CPO 212
  • 4.5.4    Glass Core (Interposer) Package: Process Flow     212
  • 4.5.5    Challenges of Glass Packaging         214
    • 4.5.5.1 Handling and Breakage           214
    • 4.5.5.2 Via Formation and Metallisation       214
    • 4.5.5.3 Thermal Conductivity               214
    • 4.5.5.4 RDL Adhesion                214
    • 4.5.5.5 Warpage Control         214
• 4.6        3D Advanced Semiconductor Packaging Technologies     220
  • 4.6.1    Evolution of Bumping Technologies 220
    • 4.6.1.1 Solder Bumps (C4)     220
    • 4.6.1.2 Copper Pillar Bumps 220
    • 4.6.1.3 Micro-Bumps 220
    • 4.6.1.4 Hybrid Bonding (Bumpless) 220
  • 4.6.2    Challenges in Scaling Bumps             220
    • 4.6.2.1 Mechanical Challenges          220
    • 4.6.2.2 Electrical Challenges               221
    • 4.6.2.3 Manufacturing Challenges   221
    • 4.6.2.4 Implications for CPO 221
  • 4.6.3    Micro-Bump for Advanced Semiconductor Packaging      224
    • 4.6.3.1 Micro-Bump Structure             224
  • 4.6.4    Bumpless Cu-Cu Hybrid Bonding    224
    • 4.6.4.1 Hybrid Bonding Concept        224
    • 4.6.4.2 Process Fundamentals           224
    • 4.6.4.3 Key Characteristics   224
    • 4.6.4.4 Benefits for CPO          225
  • 4.6.5    Three Ways of Cu-Cu Hybrid Bonding: Benchmark              225
    • 4.6.5.1 Die-to-Die (D2D)         225
    • 4.6.5.2 Die-to-Wafer (D2W)  225
    • 4.6.5.3 Wafer-to-Wafer (W2W)            225
  • 4.6.6    Challenges in Cu-Cu Hybrid Bonding Manufacturing Process      227
• 4.7        CPO Packaging: EIC and PIC Integration      231
  • 4.7.1    EIC/PIC Integration by Conventional Interconnect Techniques    231
    • 4.7.1.1 Wire Bond Integration               231
    • 4.7.1.2 Flip-Chip Integration (2D)      232
  • 4.7.2    EIC/PIC Integration by Emerging Interconnect Techniques              234
    • 4.7.2.1 2.5D Interposer Integration   234
    • 4.7.2.2 3D Micro-Bump Stacking       234
    • 4.7.2.3 3D Hybrid Bonding     234
  • 4.7.3    2D to 3D EIC/PIC Integration Options            236
    • 4.7.3.1 Technology Transition Drivers             238
    • 4.7.3.2 2D to 3D Integration Evolution            239
  • 4.7.4    Integration Roadmap by CPO Segment        240
  • 4.7.5    Benchmarking of Different Packaging Technologies for EIC/PIC  241
  • 4.7.6    Pros and Cons of 2D Integration of EIC/PIC               241
  • 4.7.7    Pros and Cons of 2.5D Integration of EIC/PIC           242
  • 4.7.8    Pros and Cons of 3D Hybrid Integration of EIC/PIC               243
  • 4.7.9    Pros and Cons of 3D Monolithic Integration of EIC/PIC      244
• 4.8        TSV for EIC/PIC Integration   245
  • 4.8.1    TSV for EIC/PIC Integration in CPO  245
    • 4.8.1.1 TSV Configurations for EIC/PIC          245
    • 4.8.1.2 Design Considerations            245
  • 4.8.2    Benefits of TSV for PIC/EIC Integration          246
  • 4.8.3    Cisco Packaging Architectures of Optical Engine Over Generations         247
  • 4.8.4    Cisco: 2.5D Chip-on-Chip (CoC) Packaging Architecture for EIC/PIC Integration            248
    • 4.8.4.1 Architecture Description        248
    • 4.8.4.2 Manufacturing Considerations          248
  • 4.8.5    Cisco: 3D TSV for PIC/EIC Integration            249
    • 4.8.5.1 Architecture Description        249
    • 4.8.5.2 Benefits of TSV Integration    249
    • 4.8.5.3 Manufacturing Considerations          249
  • 4.8.6    Key TSV Fabrication Steps and Challenges in CPO               249
    • 4.8.6.1 Fabrication Process Flow      250
  • 4.8.7    Packaging Options for Silicon Photonics     251
  • 4.8.8    Pros and Cons of 2.5D Si Interposer for EIC/PIC Integration           251
• 4.9        Fan-Out for EIC/PIC Integration         252
  • 4.9.1    ASE's Proposed Fan-Out Solution for CPO Packaging        252
    • 4.9.1.1 ASE Fan-Out CPO Concept  252
  • 4.9.2    FOPOP from ASE: Process    253
  • 4.9.3    Analysis of FOPOP vs. Wire Bond Packaging for CPO          254
  • 4.9.4    Optical Packaging Process Considerations for Silicon Photonics - ASE  255
  • 4.9.5    SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO        256
  • 4.9.6    Process Flow of Integrating PIC and EIC in a FOEB Structure         257
  • 4.9.7    Process Challenges in Packaging Optical Engines                258
  • 4.9.8    Challenges of Using Fan-Out for EIC/PIC Integration          258
• 4.10     Glass-Based CPO Packaging Technologies               259
  • 4.10.1 Glass-Based Co-Packaged Optics  259
    • 4.10.1.1            Corning's Glass CPO Vision 259
  • 4.10.2 Glass CPO Package Architecture      260
  • 4.10.3 Glass-Based CPO Process Development    261
    • 4.10.3.1            Corning's 102.4 Tb/s Test Vehicle Demonstration 262
• 4.11     Hybrid Bonding for EIC/PIC Integration         262
  • 4.11.1 TSMC: Integrated HPC Technology Platform for AI 262
  • 4.11.2 iOIS: Integrated Optical Interconnection System from TSMC        263
  • 4.11.3 Combining EIC and PIC with 3D SoIC Bond               264
  • 4.11.4 Roadmap of Bond Pitch Scaling        265
• 4.12     System Integration of Optical Engine and ASIC/XPU            266
  • 4.12.1 Co-Packaging vs. Co-Packaged Optics (CPO)         266
  • 4.12.2 Three Types of CPO + XPU/Switch ASIC Packaging Structures      267
    • 4.12.2.1            Type 1: 2D/2.5D Peripheral Integration          267
    • 4.12.2.2            Type 2: 2.5D with Embedded Bridge               267
    • 4.12.2.3            Type 3: 3D Stacked Integration           267
• 4.13     Future 3D-CPO Structure       268
  • 4.13.1 Future 3D-CPO Architecture Vision 268
  • 4.13.2 NVIDIA's 3D Integration of SoC, HBM, EIC, and PIC on Co-Packaged Substrates             272
    • 4.13.2.1.1        Architecture Overview             272
    • 4.13.2.1.2        Integration Approach                272
    • 4.13.2.1.3        Key Innovations            272
• 4.14     Optical Alignment and Laser Integration     273
  • 4.14.1 How CPO is Built and the Bottleneck             273
  • 4.14.2 The fibre attach bottleneck   273
  • 4.14.3 Interface Between Coupler and FAU              274
  • 4.14.4 Grating vs. Edge Couplers: Challenges in High-Density Optical I/O for Silicon Photonics          275
  • 4.14.5 Challenges in High-Density Optical I/O for Silicon Photonics       276
• 4.15     Fiber Array Unit (FAU)               277
  • 4.15.1 Optical Alignment Challenges and Solutions           277
  • 4.15.2 Two Alignment Approaches 278
  • 4.15.3 Reducing Optical Fiber Packaging Complexity        279
  • 4.15.4 Key Technical Challenges      279
    • 4.15.4.1            The Size Mismatch Between Silicon Waveguides and Planar Optical Fibers        279
  • 4.15.5 Fiber Attach Methods               280
  • 4.15.6 Key Players in FAU for CPO   282
  • 4.15.7 Benchmark of Optical Fiber Alignment Structure Variations          282
  • 4.15.8 Suppliers of Other Optical Components in CPO    284
• 4.16     Suppliers of Other Optical Components in CPO    284
• 4.17     Laser Integration          289
  • 4.17.1 On-Chip Light Source Integration Methods                289
  • 4.17.2 External Lasers for CPO          290
  • 4.17.3 Laser Attach Technology Benchmark            294
  • 4.17.4 Benchmark of Different Laser Integration Technologies    295

5             CO-PACKAGED OPTICS MARKET ANALYSIS               297

• 5.1        CPO Market Definition and Scope    297
• 5.2        CPO Market Size and Growth Projections   297
• 5.3        Switch CPO Market Analysis               298
  • 5.3.1    Market Overview and Drivers               298
  • 5.3.2    Deployment Timeline and Adoption Phases             298
  • 5.3.3    Volume Projections and Market Sizing          298
  • 5.3.4    Market Concentration and Regional Distribution   299
  • 5.3.5    Pricing Trajectory and Cost Dynamics          300
• 5.4        XPU Optical I/O Market Analysis       300
  • 5.4.1    Market Drivers and Value Proposition           300
  • 5.4.2    Adoption Timeline and Platform Evolution 301
  • 5.4.3    Volume and Revenue Projections     301
  • 5.4.4    Market Segmentation by Platform    302
  • 5.4.5    Technology Requirements and Differentiation         302
• 5.5        CPO Pricing and Cost Analysis          303
  • 5.5.1    Current Pricing Landscape   303
  • 5.5.2    Cost Trajectory and Reduction Drivers          303
  • 5.5.3    Cost Parity Timeline and Dynamics 304
  • 5.5.4    Pricing Strategy Implications               305
• 5.6        Regional Market Dynamics   305
  • 5.6.1    North America              305
  • 5.6.2    Asia-Pacific    306
  • 5.6.3    Europe                307
  • 5.6.4    Rest of World 307
• 5.7        Total Addressable Market Analysis  308
  • 5.7.1    Core TAM Segments  308
  • 5.7.2    Serviceable Addressable Market (SAM)       309
• 5.8        Market Forecast by Component        310
• 5.9        Market Forecast by Technology Generation               311
  • 5.9.1    Optical Engine Bandwidth Evolution              311
  • 5.9.2    Generation Lifecycle Analysis            311
• 5.10     Market Restraints and Barriers           312
  • 5.10.1 Manufacturing Yield and Cost            312
  • 5.10.2 Serviceability and Field Replacement Concerns    313
  • 5.10.3 Standards Maturity and Interoperability       314
  • 5.10.4 Supply Chain Capacity Constraints               314
  • 5.10.5 Competitive Alternatives        315
• 5.11     Adoption Curve Analysis        316
  • 5.11.1 Technology Adoption Framework     316
    • 5.11.1.1            Innovators (2024-2026)          316
    • 5.11.1.2            Early Adopters (2026-2028) 317
    • 5.11.1.3            Early Majority (2028-2031)   318
    • 5.11.1.4            Late Majority (2031-2034)     318
    • 5.11.1.5            Laggards (2034+)        319
  • 5.11.2 Segment-Specific Adoption Curves                319
• 5.12     Adoption Accelerators and Inhibitors            320
  • 5.12.1 Adoption Curve Implications               320
• 5.13     Competitive Landscape Evolution   321
  • 5.13.1 Current Competitive Positioning      321
  • 5.13.2 Integrated Device Manufacturers (IDMs)     321
  • 5.13.3 Silicon Photonics Specialists              321
  • 5.13.4 Foundry/OSAT Providers         321
  • 5.13.5 System Vendors           321
  • 5.13.6 Laser Suppliers             322
  • 5.13.7 Competitive Dynamics and Market Structure Evolution    322
    • 5.13.7.1            Near-Term Dynamics (2025-2028)  322
      • 5.13.7.1.1        Expected Evolution (2028)    323
    • 5.13.7.2            Mid-Term Dynamics (2028-2032)     323
      • 5.13.7.2.1        Expected Evolution (2032)    323
    • 5.13.7.3            Long-Term Dynamics (2032-2036)  323
      • 5.13.7.3.1        Expected Evolution (2036)    324
  • 5.13.8 Vertical Integration Trends    324
    • 5.13.8.1            Integration Strategy Framework         324
      • 5.13.8.1.1        Full Vertical Integration (Broadcom, Intel Model)   324
      • 5.13.8.1.2        Partial Integration (Cisco, NVIDIA Model)    325
      • 5.13.8.1.3        Fabless/Assembly-Light (Ayar Labs, Ranovus Model)         325
      • 5.13.8.1.4        Platform Provider (TSMC Model)       326
    • 5.13.8.2            Strategic Implications of Integration Trends              327
• 5.14     Scenario Analysis       328
  • 5.14.1 Scenario Framework 328
  • 5.14.2 Scenario Definitions 328
  • 5.14.3 Bull Case Scenario     328
  • 5.14.4 Base Case Scenario  329
  • 5.14.5 Bear Case Scenario   330
  • 5.14.6 Scenario Comparison and Key Variables    332

6             GLOBAL MARKET TRENDS IN DATACOM     333

• 6.1        Introduction to DATACOM Market Dynamics            333
  • 6.1.1    Overview of the Data Communications Market       333
    • 6.1.1.1 Market Definition and Scope               333
    • 6.1.1.2 Market Size and Growth          333
  • 6.1.2    Key Market Drivers      333
    • 6.1.2.1 Artificial Intelligence and Machine Learning             333
    • 6.1.2.2 Cloud Computing Growth     334
    • 6.1.2.3 Data Growth   334
    • 6.1.2.4 Power and Sustainability Pressures                334
• 6.2        Application Trends     335
  • 6.2.1    AI and Machine Learning Workload Growth               335
    • 6.2.1.1 The AI Training Revolution     335
    • 6.2.1.2 Training Cluster Architecture Evolution        335
    • 6.2.1.3 AI Inference Deployment        335
    • 6.2.1.4 Market Quantification              336
    • 6.2.1.5 Implications for CPO 336
  • 6.2.2    Hyperscale Data Centre Expansion 336
    • 6.2.2.1 Defining Hyperscale  336
  • 6.2.3    Global Hyperscale Capacity                336
  • 6.2.4    Regional Distribution                337
  • 6.2.5    Hyperscaler Investment Trends         337
    • 6.2.5.1 Capital expenditure acceleration     337
    • 6.2.5.2 AI-Specific Infrastructure       337
    • 6.2.5.3 Implications for CPO 337
  • 6.2.6    Edge Computing and Distributed AI                337
    • 6.2.6.1 Market Growth              338
  • 6.2.7    Edge AI Applications 338
  • 6.2.8    Edge Network Architecture   338
• 6.3        Technology Trends      339
  • 6.3.1    Technology Trends Overview               339
    • 6.3.1.1 Key Technology Vectors          339
    • 6.3.1.2 Technology Interdependencies          339
  • 6.3.2    Technology Trends: Packaging           340
  • 6.3.3    Universal Chiplet Interconnect Express (UCIe)       341
  • 6.3.4    Laser Sources for CPO            341
  • 6.3.5    External vs. Integrated Laser                342

7             MARKET OUTLOOK    344

• 7.1        Scale-Out Outlook     344
  • 7.1.1    Scale-Out CPO Market Evolution     344
    • 7.1.1.1 Scale-Out Market Drivers       344
    • 7.1.1.2 Market Evolution Phases        344
    • 7.1.1.3 Scale-Out CPO Market Forecast       344
  • 7.1.2    Scale-Out Technology Roadmap      345
    • 7.1.2.1 Technology Generation Evolution     345
    • 7.1.2.2 Technology Enablers by Generation                346
  • 7.1.3    Scale-Out Key Players and Competitive Landscape            346
• 7.2        Scale-Up Outlook       347
  • 7.2.1    Scale-Up CPO Market Evolution       347
  • 7.2.2    Copper to Optical Transition               347
  • 7.2.3    Optical I/O Solution   348
  • 7.2.4    Scale-Up CPO Market Forecast         348
  • 7.2.5    Market Evolution Phases        348
  • 7.2.6    Scale-Up Technology Roadmap        349
    • 7.2.6.1 NVIDIA Optical I/O Evolution               350
    • 7.2.6.2 AMD Optical I/O Evolution    350
    • 7.2.6.3 Custom Silicon Optical I/O   350
  • 7.2.7    Scale-Up Key Players and Competitive Landscape              352
    • 7.2.7.1 Competitive Landscape Overview   352
• 7.3        High-Density Connectors      352
  • 7.3.1    High-Density Connectors vs. CPO   352
    • 7.3.1.1 Scenario 1: Connectors Enable Extended Pluggable (Low CPO Impact) 352
    • 7.3.1.2 Scenario 2: Connectors Complement CPO (Moderate Impact)   353
    • 7.3.1.3 Scenario 3: Connectors Enable "Near-Packaged" Optics (Moderate CPO Impact)         353
    • 7.3.1.4 Scenario 4: Connector Development Delays (Positive CPO Impact)        353
• 7.4        Emerging Supply Chain Dynamics   357
  • 7.4.1    Geographic Concentration in CPO Supply Chains                358
• 7.5        Third-Party Suppliers and Systems Integrators        360
  • 7.5.1    Multi-Tier Supply Chain Architecture              360
    • 7.5.1.1 Tier 1: Silicon Photonics Platform     360
    • 7.5.1.2 Tier 2: CPO Assembly (OSAT)              361
    • 7.5.1.3 Tier 3: Fiber Array Unit (FAU) Suppliers          361
    • 7.5.1.4 Tier 4: External Laser Source (ELS) Suppliers            362
    • 7.5.1.5 Tier 5: Optical Fiber Supply   362
    • 7.5.1.6 Tier 6: Optical Sub-Assembly Integration    362
  • 7.5.2    Strategic Implications for Supply Chain Participants          362

8             COMPANY PROFILES                364 (61 company profiles)

9             APPENDIX        430

• 9.1        Research Methodology and Data Sources  430

10          REFERENCES 431

List of Tables

• Table 1. CPO Market Drivers and Restraints Analysis         37
• Table 2. Key Data Centre Architecture Challenges Summary        41
• Table 3. Key Data Centre Architecture Challenges Summary.       44
• Table 4. Form Factor Evolution and Density Comparison 46
• Table 5. Optical Transceiver Power Consumption by Generation 47
• Table 6. Technology Migration Decision Framework             47
• Table 7. CPO vs. Pluggables Decision Matrix             49
• Table 8. Semiconductor Packaging Interconnection Techniques Overview          54
• Table 9. CPO Application Segmentation (Scale-Out vs. Scale-Up)             56
• Table 10. EIC/PIC Integration Methods Comparison           57
• Table 11. Integration Technology Selection Criteria              61
• Table 12. Detailed Technical Comparison: 2D vs 2.5D vs 3D         62
• Table 13. 3D Integration Sub-Categories Comparison       62
• Table 14. Packaging Technology Benchmark for EIC/PIC Integration        63
• Table 15. CPO Technology Challenges and Mitigation Strategies 68
• Table 16. NVIDIA vs. Broadcom Strategic Positioning Comparison           69
• Table 17. NVIDIA vs. Broadcom CPO Product Specifications Benchmark             70
• Table 18. Server Boards, CPUs, and GPU/Accelerator Forecast (2026-2036)     72
• Table 19. Optical I/O CPO Unit Shipment Forecast (2026-2036) 73
• Table 20. Optical I/O CPO Revenue Forecast (2026-2036)              73
• Table 21. CPO Network Switch Unit Shipment Forecast    74
• Table 22. CPO Network Switch Revenue Forecast (2026-2036)   75
• Table 23. Total CPO Market Size and Revenue (2026-2036)            76
• Table 24. CPO Unit Shipments by Integration Technology 77
• Table 25. Network Switch CPO Adoption by Packaging Technology           78
• Table 26. Optical I/O Forecast by Packaging Technology  79
• Table 27. PIC Design Segment - Key Players and Capabilities       80
• Table 28. ASIC and xPU Design Segment - Key Players and CPO Integration Strategies                81
• Table 29. Laser Sources Segment - Key Suppliers and Technologies        82
• Table 30. SOI Wafer and Epi-Wafer Segment - Substrate Suppliers            83
• Table 31. EIC, Retimers, SerDes, and PHY Segment - High-Speed Electronics Suppliers           83
• Table 32. Connectors and Fibers Segment - Optical Infrastructure Suppliers     84
• Table 33. Foundries Segment - Silicon Photonics and Advanced Packaging Capabilities          85
• Table 34. Packaging, Assembling, and Testing Segment - OSAT and Test Equipment Providers              85
• Table 35. System and Equipment Segment - OEMs and ODMs    86
• Table 36. End Customers (Hyperscalers) Segment - Data Centre Operators and AI Leaders    87
• Table 37. CPO Industrial Ecosystem Summary - Complete Value Chain Overview         88
• Table 38. AI Model Parameter and Compute Growth (2018-2030)             90
• Table 39. Global AI Training Compute Demand Growth     91
• Table 40. AI Data Centre Requirements by Workload Type               93
• Table 41. Switch Hierarchy in AI Data Centres          96
• Table 42. Scale-Up vs. Scale-Out vs. Scale-Across Comparison Matrix 99
• Table 43. SerDes Bandwidth Limitations and Power Consumption           102
• Table 44. SerDes Bottleneck Solutions Comparison           103
• Table 45. Pluggable Optics Architecture and Limitations 104
• Table 46. Signal Loss Comparison: Pluggable vs. CPO (dB)            109
• Table 47. Comprehensive Pluggable vs. CPO Comparison             109
• Table 48. Design Decision Framework for CPO Adoption 110
• Table 49. L2 Network Architecture Comparison     112
• Table 50.Copper Wire Count in Current AI Systems             113
• Table 51. Copper Interconnect Specifications by System 114
• Table 52. Copper System Limitations Summary     115
• Table 53. Copper vs. Optical Performance Benchmark     116
• Table 54. Power Consumption by Interconnect Technology            122
• Table 55. Power Consumption Component Breakdown: Pluggable vs. CPO (400G)       122
• Table 56. Latency Benchmark Comparison               123
• Table 57. PIC Component Overview               129
• Table 58. PICs vs. Silicon Photonics Comparison 130
• Table 59. Silicon Photonics vs. Other PIC Platforms: Capability Comparison    130
• Table 60. PIC Advantages and Challenges Summary          134
• Table 61. Optical Engine vs. Pluggable Transceiver Comparison 135
• Table 62. External Laser Source Configurations     137
• Table 63. CPO Technology Building Blocks 141
• Table 64. CPO Technology Components and Suppliers     141
• Table 65. Latency Comparison: Pluggable vs. CPO              143
• Table 66. Data Rate Scaling: Pluggable vs. CPO      145
• Table 67. CPO Value Proposition Summary               146
• Table 68. CPO Technical Challenges and Mitigation Approaches               147
• Table 69. OIF CPO Standards Development Timeline         148
• Table 70. OIF CPO Framework Functional Partitioning      149
• Table 71. OIF CPO Module Specifications by Generation 149
• Table 72. ELSFP Implementation Agreement Key Specifications 150
• Table 73. CPO Telemetry and Management Requirements              150
• Table 74. OIF CEI Specifications for CPO Applications      151
• Table 75. UCIe Specifications and CPO Relationship         152
• Table 76. China CPO Standards Landscape              152
• Table 77. CPO Component Packaging Requirements         155
• Table 78. Switch CPO Package Specifications (Representative)  157
• Table 79. 1.6 Tbps Optical Engine Performance      158
• Table 80. XPU Optical I/O Requirements     159
• Table 81. Advanced Optical I/O Integration Approaches   161
• Table 82.Overview of CPO Packaging Technologies             166
• Table 83. Semiconductor Packaging Technology Landscape         170
• Table 84. Packaging Technology Comparison for CPO        171
• Table 85. Advanced Packaging Performance Metrics          172
• Table 86. Overview of Interconnection Techniques in Semiconductor Packaging            176
• Table 87.  Interconnection Technique Comparison for CPO           178
• Table 88. Silicon Interposer vs. Silicon Bridge Comparison            180
• Table 89. Silicon-Based 2.5D Packaging Options  181
• Table 90. TSV Specifications by Application              184
• Table 91. TSV Fabrication Process Steps     184
• Table 92.TSV Technology Evolution  185
• Table 93. TSV Challenges for CPO Applications      185
• Table 94. TSV Technology Evolution.              187
• Table 95. 2.5D Silicon Packaging Development Trends      188
• Table 96. Key Development Areas by Technology Node     190
• Table 97. Interposer Size Evolution for CPO               190
• Table 98. 2.5D Silicon Packaging Roadmap by Vendor       192
• Table 99. Roadmap Milestones for CPO Integration             192
• Table 100. Si Interposer vs. Si Bridge Comparison 192
• Table 101. RDL Technology Specifications 195
• Table 102. SiO2 vs. Organic Dielectric Comparison            197
• Table 103. WLFO vs. PLFO Comparison      200
• Table 104. Fan-Out Packaging Trends           202
• Table 105. Fan-Out Process Challenges      204
• Table 106. Glass Properties vs. Silicon and Organic.           207
• Table 107. Glass Applications in Semiconductor Packaging         208
• Table 108. Glass Core Interposer Characteristics 209
• Table 109. Glass vs. Silicon Interposer Comparison           211
• Table 110. Glass Interposer Benefits for CPO           211
• Table 111. Glass vs. Molding Compound Properties            211
• Table 112. Glass Packaging Challenges and Solutions      216
• Table 113. Bumping Technology Evolution 220
• Table 114. Bump Scaling Challenges             222
• Table 115. Micro-Bump Specifications and Applications 224
• Table 116. Cu-Cu Hybrid Bonding Methods Comparison 226
• Table 117. Hybrid Bonding Method Selection for CPO Applications          226
• Table 118. Hybrid Bonding Manufacturing Challenges       228
• Table 119. Hybrid Bonding Process Maturity by Pitch          231
• Table 120. Critical Process Parameters for Hybrid Bonding            231
• Table 121. Conventional EIC/PIC Integration Methods       232
• Table 122. Conventional Method Advantages and Limitations Summary              233
• Table 123. Emerging EIC/PIC Integration Methods 235
• Table 124. 2D to 3D EIC/PIC Integration Options   237
• Table 125. Technology Transition Drivers     239
• Table 126. 2D to 3D Integration Evolution   240
• Table 127. Integration Roadmap by CPO Segment                240
• Table 128. EIC/PIC Packaging Technology Benchmark      241
• Table 129. 2D EIC/PIC Integration Pros and Cons  241
• Table 130. 2.5D EIC/PIC Integration Pros and Cons             242
• Table 131. 3D Hybrid EIC/PIC Integration Pros and Cons 243
• Table 132. 3D Monolithic EIC/PIC Integration Pros and Cons        244
• Table 133. Benefits of TSV for PIC/EIC Integration 247
• Table 134. TSV Fabrication Challenges in CPO        250
• Table 135. Si Photonics Packaging Options Comparison 251
• Table 136. 2.5D Si Interposer Pros and Cons for EIC/PIC  251
• Table 137. FOPOP vs. WB Packaging Comparison 254
• Table 138. Optical Engine Packaging Process Challenges               258
• Table 139. Fan-Out EIC/PIC Integration Challenges             258
• Table 140. Bond Pitch Scaling Challenges  266
• Table 141. Co-Packaging vs. CPO Definition Comparison               266
• Table 142. Future 3D-CPO Architecture Vision        268
• Table 143. Architecture Evolution by Component 269
• Table 144. 3D-CPO Integration Approaches              269
• Table 145. Future 3D-CPO Packaging Structure Types       270
• Table 146. Key Technology Milestones for Future 3D-CPO              270
• Table 147. Performance Trajectory for Future 3D-CPO      271
• Table 148. Thermal Management Evolution for 3D-CPO   271
• Table 149.3D-CPO Vision: NVIDIA Architecture Example 272
• Table 150. CPO Assembly Process and Bottlenecks            273
• Table 151. Coupler-FAU Interface Critical Dimensions      274
• Table 152. Misalignment Loss Characterisation     274
• Table 153. FAU-PIC Interface Stability Requirements         275
• Table 154. Grating vs. Edge Coupler Comparison 275
• Table 155. Grating vs. Edge Coupler Comparison 276
• Table 156. Optical Alignment Challenges Overview             277
• Table 157. Active vs. Passive Alignment Comparison         278
• Table 158. Fiber Attach Methods Comparison        281
• Table 159. FAU Supplier Landscape               282
• Table 160. Alignment Structure Benchmark              283
• Table 161. SENKO Key CPO Solutions           284
• Table 162. Suppliers of Optical Components in CPO: Comprehensive Overview             285
• Table 163. Laser Source Supplier Details    289
• Table 164. On-Chip Laser Integration Approaches               290
• Table 165. External Laser Configurations for CPO 291
• Table 166. External Laser Suppliers 293
• Table 167. Laser Attach Technology Comparison  294
• Table 168. Comprehensive Laser Integration Benchmark 296
• Table 169. Global CPO Market Forecast ($ Millions)            297
• Table 170.Switch CPO Unit Volume Forecast (Thousands of Optical Engines)  299
• Table 171. Switch CPO Market Forecast by Switch Generation ($M)         299
• Table 172. CPO Cost Trajectory Projection 300
• Table 173. XPU Optical I/O Market Forecast              301
• Table 174. XPU Optical I/O Market Forecast by Platform ($M)       302
• Table 175. CPO Cost Trajectory Projection 303
• Table 176. Total Cost of Ownership Comparison (Per 51.2T Switch, 5-Year Lifetime)    304
• Table 177. North America CPO Market Forecast    305
• Table 178.Asia-Pacific CPO Market Forecast            306
• Table 179. Europe CPO Market Forecast     307
• Table 180. Rest of World CPO Market Forecast       308
• Table 181. Global CPO Market Summary    308
• Table 182. CPO Total Addressable Market Quantification 309
• Table 183.CPO Serviceable Addressable Market    309
• Table 184. CPO Component Market Forecast ($M)              310
• Table 185. CPO Market by Optical Engine Generation ($M)             311
• Table 186. Generation Share Evolution         311
• Table 187. Manufacturing Yield Improvement Trajectory  313
• Table 188. CPO Standards Development Timeline               314
• Table 189. Market Restraints Summary        316
• Table 190. CPO Adoption Curve by Segment (Penetration of Addressable Market)         319
• Table 191. CPO Market Share by Participant (2024-2026) 322
• Table 192. Near-Term Competitive Evolution            323
• Table 193. Competitive Landscape Evolution Timeline      324
• Table 194. Vertical Integration Trends by Participant Type                326
• Table 195. Vertical Integration by Company              326
• Table 196. Bull Case Market Forecast ($M) 329
• Table 197. Base Case Market Forecast ($M)             330
• Table 198. Bear Case Market Forecast ($M)              331
• Table 199. Scenario Comparison Summary              332
• Table 200. Global DATACOM Market Size and Growth        333
• Table 201. DATACOM Market Growth Drivers            334
• Table 202. Global Hyperscale Data Centre Capacity           336
• Table 203. Edge Computing Market Growth               338
• Table 204. DATACOM Technology Trends Summary             339
• Table 205. Packaging Technology Evolution for DATACOM              340
• Table 206. UCIe Specifications and Adoption Timeline      341
• Table 207. Laser Source Technology Trends              342
• Table 208. Laser Source Comparison for CPO         342
• Table 209. Scale-Out CPO Market Forecast by Switch Bandwidth ($M)  344
• Table 210. Scale-Out Technology Enablers by Generation               346
• Table 211. Scale-Out CPO Competitive Landscape             347
• Table 212. Scale-Up CPO Market Forecast by Platform ($M)          348
• Table 213. Scale-Up CPO Market Forecast 349
• Table 214. Scale-Up CPO Market Evolution Phases             349
• Table 215. Scale-Up CPO Platform Comparison    349
• Table 216. Scale-Up vs. Scale-Out CPO Comparison         351
• Table 217. Scale-Up CPO Competitive Landscape               352
• Table 218. CPO vs. High-Density Connector Adoption Scenarios               353
• Table 219. OIF High-Density Connector Specifications (Proposed)           354
• Table 220. Technology Comparison: CPO vs. High-Density Connector-Enabled Alternatives   355
• Table 221. Scenario Impact by Market Segment     355
• Table 222. High-Density Connector Development Roadmap vs. CPO Timeline 356
• Table 223. Why High-Density Connectors Are Unlikely to Derail CPO      356
• Table 224. Scenario Summary and Strategic Implications               357
• Table 225. NVIDIA CPO Supply Chain Geographic Distribution    358
• Table 226. Taiwan IC Industry Market Share Evolution (2021-2025)          358
• Table 227. TSMC COUPE Platform Technical Specifications           360
• Table 228. External Laser Source Suppliers for NVIDIA CPO          362

List of Figures

• Figure 1. Anatomy of a Modern AI Data Centre         39
• Figure 2. Network Switch Architecture in Data Centres     40
• Figure 3. Switch IC Bandwidth Evolution Timeline (2015-2036)   43
• Figure 4. Optical Transceiver Technology Migration Path (Pluggable → Near-Package → CPO)  46
• Figure 5. Optical Engine Component Architecture                50
• Figure 6. Co-Packaged Optics 1.0: Typical Integration Flow.          51
• Figure 7. Heterogeneous Integration Concept Diagram    52
• Figure 8. Evolution from 2D to 2.5D to 3D Integration          60
• Figure 9. Integration Technology Progression Roadmap    60
• Figure 10. Optical I/O CPO Unit Shipment Forecast (2026-2036)               73
• Figure 11. Optical I/O CPO Revenue Forecast (2026-2036)            74
• Figure 12. CPO Network Switch Unit Shipment Forecast  75
• Figure 13. CPO Network Switch Revenue Forecast (2026-2036). 76
• Figure 14. Total CPO Market Size and Revenue (2026-2036)          77
• Figure 15. CPO Unit Shipments by Integration Technology              78
• Figure 16. Switch ASIC with pluggable optics versus co-packaged optics            81
• Figure 17. LLM Parameter Growth Timeline (GPT-1 to GPT-5 and Beyond)             91
• Figure 18. DGX H100/H200system topology             94
• Figure 19. NVIDIA Rubin Architecture Overview      95
• Figure 20. Scale-Up Network Topology (NVLink, NVSwitch)            97
• Figure 21. Scale-Out and Scale-Up Network Topology (Ethernet/InfiniBand)      99
• Figure 22. Three-Tier Network Architecture Diagram           100
• Figure 23. Interconnect Technology Roadmap (2020-2036)           102
• Figure 24. On-Board Optics Configuration 106
• Figure 25. Switch ASIC Bandwidth Scaling (51.2T → 102.4T → 204.8T)     111
• Figure 26. Copper-to-Optical Migration Roadmap 118
• Figure 27. Current AI System Interconnect Architecture    119
• Figure 28. AI Architecture Evolution (2026-2030)  125
• Figure 29. AI Architecture Vision (2031-2036)          127
• Figure 30. PIC Architecture for CPO Applications  133
• Figure 31. CPO Key Concepts Illustration   139
• Figure 32. Power Consumption Comparison (pJ/bit Roadmap)   144
• Figure 33. Optical I/O Packaging for XPUs  160
• Figure 34. Schematic view of three optically enabled data center platforms (LightningValley2, ThunderValley and Pegasus) and the Aurora test and measurement platform contained within the Nexus rack, which allows intra-rack and inter-rack connectivity betwee                164
• Figure 35. Semiconductor Packaging Evolution Timeline 168
• Figure 36. 2.5D Packaging Structure Diagram          179
• Figure 37. 2.5D Si-Based Packaging Roadmap       191
• Figure 38. EMIB implementation (silicon bridge).  193
• Figure 39. FPGA + HBM in 2.5D package with interposer. 193
• Figure 40. RDL Fabrication Process Flow    196
• Figure 41. Panel-Level Fan-Out Process      199
• Figure 42. Wafer-Level Fan-Out Process      200
• Figure 43. Glass Core Interposer Structure                209
• Figure 44. Glass Interposer Manufacturing Process Flow 213
• Figure 45. (a) Switch composed of 2.5D advanced packaging; (b) TMV-based, (c) TSV-based, and (d) TGV-based advanced packaging architectures.      246
• Figure 46. ASE Fan-Out CPO Solution           253
• Figure 47. ASE FOPOP Process Flow              254
• Figure 48. SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO 257
• Figure 49. FOEB Integration Process Flow  258
• Figure 50. TSMC Optical Engine Roadmap 263
• Figure 51. TSMC iOIS Architecture   264
• Figure 52. (a) TSMC-SoIC face-to-face (F”F) technology for EIC and PIC bonding. (b) COUPE critical components consist of TSMC-SoIC bond, TDC, embedded micro-lens and metal reflector.   265
• Figure 53. Bond Pitch Scaling Roadmap      265
• Figure 54.Scale-Up Optical I/O Technology Roadmap       351

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• Comprehensive Excel spreadsheet of all data.
• Mid-year Update

The Global Co-Packaged Optics Market 2026-2036

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The Global Co-Packaged Optics Market 2026-2036

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