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The Global Co-Packaged Optics Market 2026-2036

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  • Published: May 2026
  • Pages: 443
  • Tables: 229
  • Figures: 48

 

The co-packaged optics (CPO) market addresses a structural bottleneck in AI datacentre infrastructure: as switch ASIC bandwidth doubles roughly every 18–24 months while the electrical reach of copper signalling shrinks at higher SerDes rates, conventional pluggable optical transceivers are reaching fundamental physical and economic limits. CPO resolves this by integrating the optical engine directly within the switch ASIC or GPU/XPU package, shortening the electrical path, cutting interconnect power consumption from roughly 15 picojoules per bit toward 5 pJ/bit and below, and removing the front-panel density ceiling that constrains pluggable designs at 102.4 Tbps and above.

The market comprises two sub-segments with distinct timing. Scale-out CPO — optical engines for Ethernet and InfiniBand network switches — is the earlier and more standardised segment, with first commercial deployments at hyperscalers in 2026 on Broadcom Tomahawk 6-based platforms. Scale-up CPO — optical I/O integrated within GPU packages to replace copper interconnects such as NVLink — begins its volume ramp later in the decade with the NVIDIA Rubin generation, and is widely expected to become the larger and faster-growing of the two sub-segments as GPU optical I/O attach rates rise.

Importantly, CPO is additive rather than a wholesale replacement for pluggable transceivers, which retain structural dominance in enterprise, telecom, and lower-bandwidth cloud applications throughout the forecast period. The late-2020s window is best understood as a managed coexistence of pluggable, near-package, and co-packaged optics across different datacentre tiers, with the balance shifting steadily toward integration as reliability, thermal, and interoperability challenges are resolved.

The competitive landscape spans vertically integrated leaders — NVIDIA and Broadcom — and a layer of specialist innovators. Among these, Ayar Labs is notable: the fabless optical I/O chiplet developer closed a $500 million Series E round in March 2026 led by Neuberger Berman, bringing total funding to approximately $870 million and a valuation of $3.75 billion, with strategic backing from AMD and NVIDIA. The proceeds are earmarked for scaling high-volume production and test capacity for its co-packaged optics solution. Advanced semiconductor packaging — 2.5D interposers, through-silicon vias, fan-out, glass interposers, and 3D hybrid bonding — is the critical enabling technology and the principal supply-chain bottleneck, alongside laser source capacity. NVIDIA's March 2026 investment in Lumentum and Coherent underscores how upstream silicon-photonics and laser supply have become strategically central to the CPO ecosystem.

The Global Co-Packaged Optics Market 2026-2036 delivers a comprehensive analysis of one of the most significant technological transitions in data centre infrastructure since the advent of optical communications. As switch ASIC bandwidth doubles roughly every 18–24 months while the electrical reach of copper signalling shrinks at higher SerDes rates, conventional pluggable optical transceivers are reaching fundamental physical and economic limits. Co-packaged optics (CPO) resolves this by integrating the optical engine directly within the switch ASIC or GPU/XPU package, dramatically shortening the electrical path, reducing interconnect power consumption from roughly 15 picojoules per bit toward 5 pJ/bit and below, and removing the front-panel density ceiling that constrains pluggable designs at 102.4 Tbps and above.

This report examines the market across two principal sub-segments. Scale-out CPO — optical engines for Ethernet and InfiniBand network switches — is the earlier and more standardised segment, with first commercial deployments at hyperscalers using Broadcom Tomahawk 6-based platforms. Scale-up CPO — optical I/O integrated within GPU packages to replace copper interconnects such as NVLink — ramps later in the decade with the NVIDIA Rubin generation and is expected to become the larger, faster-growing sub-segment as GPU optical I/O attach rates rise. CPO is positioned as additive rather than a wholesale replacement for pluggable transceivers, which retain structural dominance in enterprise, telecom, and lower-bandwidth cloud applications, producing a managed coexistence of pluggable, near-package, and co-packaged architectures across the forecast period.

The report provides detailed coverage of CPO technology fundamentals, photonic integrated circuits, optical engines, and the advanced semiconductor packaging that enables CPO — including 2.5D silicon, organic and glass interposers, through-silicon vias, fan-out wafer-level packaging, and 3D hybrid bonding. It analyses EIC/PIC integration approaches, optical alignment and laser integration, CPO standards, the competitive divergence between NVIDIA's vertical integration and Broadcom's open-ecosystem strategy, supply-chain structure, regional dynamics, adoption-curve and scenario analysis, and ten-year market forecasts by application, component, technology generation, and packaging technology. Drawing on extensive primary research and industry interviews, it offers strategic intelligence for semiconductor professionals, investors, data centre operators, and technology strategists seeking to understand how CPO will reshape AI and data centre architecture through 2036.

Report Contents

  • Executive summary, market definition, scope, and key drivers and restraints
  • Modern high-performance AI data centre architecture, switches, and switch ASIC bandwidth scaling
  • Optical transceiver trends, pluggable vs. CPO design decisions, and the optical engine
  • Heterogeneous integration, interconnection techniques, and key CPO applications (network switch and computing optical I/O)
  • EIC/PIC integration and 2D-to-3D integration options
  • CPO + XPU/switch ASIC packaging structures and challenges
  • NVIDIA vs. Broadcom strategic comparison and CPO product benchmark
  • Current and future AI system architecture
  • Ten-year market forecasts: units shipped and revenue for optical I/O and CPO network switches; total CPO market; forecasts by integration technology and packaging technology
  • CPO industrial ecosystem and value-chain analysis
  • Challenges and solutions for future AI systems: LLM growth, scale-up/scale-out/scale-across networks, SerDes bottlenecks, copper-to-optical migration, power efficiency and latency benchmarks
  • Introduction to CPO: PICs, optical engines, optical power supplies, benefits, and standards
  • Packaging for CPO: 2.5D silicon, organic and glass technologies; 3D advanced packaging; TSV, fan-out, hybrid bonding; optical alignment, fiber array units, and laser integration
  • CPO market analysis: switch CPO, XPU optical I/O, pricing and cost, regional dynamics, TAM, market restraints, adoption curve, competitive landscape, and scenario analysis
  • Global datacom market trends and market outlook for scale-out and scale-up
  • High-density connectors, emerging supply-chain dynamics, and systems integrators
  • Company profiles including Alphawave Semi, AMD, Amkor Technology, ASE Technology Holdings, Astera Labs, Avicena, AXT, Ayar Labs, Broadcom, CEA-Leti, Celestial AI, Cisco, Coherent, Corning, Credo, DenseLight, EFFECT Photonics, EVG, Fabrinet, FOCI (Fiber Optical Communication Inc.), FormFactor, Foxconn, Furukawa Electric, GlobalFoundries, Henkel, Hewlett Packard Enterprise, Hisense Broadband Multimedia Technologies, IBM, imec, Intel, JCET Group, Kyocera, Lightmatter, LioniX International, Lumentum, MACOM, Marvell, MediaTek, Molex, NVIDIA, OpenLight, POET Technologies and more....

 

 

1             EXECUTIVE SUMMARY            35

  • 1.1        Report Overview and Key Findings   35
  • 1.2        Market Definition and Scope               35
    • 1.2.1    Definition of Co-Packaged Optics (CPO)     35
    • 1.2.2    Scope of This Report 36
  • 1.3        Key Market Drivers and Restraints   36
  • 1.4        Modern High-Performance AI Data Centre Architecture    37
    • 1.4.1    Physical Infrastructure Hierarchy     37
    • 1.4.2    Network Architecture                38
    • 1.4.3    Power and Cooling Considerations 38
  • 1.5        Switches: Key Components in Modern Data Centres          39
    • 1.5.1    Switch Architecture Evolution            39
    • 1.5.2    Switch ASIC Technology         40
    • 1.5.3    Optical Transceiver Requirements   41
  • 1.6        Advancements in Switch IC Bandwidth and the Need for CPO Technology          41
    • 1.6.1    Historical Bandwidth Scaling              41
    • 1.6.2    SerDes Technology Evolution              42
    • 1.6.3    Electrical Signalling Limits    42
    • 1.6.4    Front-Panel Density Constraints      42
    • 1.6.5    Power Consumption Trajectory         42
  • 1.7        Overview of Key Challenges in Data Centre Architectures               43
    • 1.7.1    Thermal Management             43
    • 1.7.2    Power Delivery              43
    • 1.7.3    Cable Management   43
    • 1.7.4    Reliability and Serviceability                44
    • 1.7.5    Standards and Interoperability           44
  • 1.8        Key Trend of Optical Transceivers in High-End Data Centres          44
    • 1.8.1    Historical Evolution   44
    • 1.8.2    Technology Migration Path    45
  • 1.9        Design Decisions: CPO vs. Pluggables Comparison           48
    • 1.9.1    Performance Comparison    48
    • 1.9.2    Operational Comparison       48
    • 1.9.3    Economic Comparison           48
  • 1.10     What is an Optical Engine (OE)?       49
    • 1.10.1 Functional Description            49
    • 1.10.2 Optical Engine Components               49
    • 1.10.3 Performance Parameters       50
  • 1.11     Heterogeneous Integration and Co-Packaged Optics         50
    • 1.11.1 The Heterogeneous Integration Imperative 51
    • 1.11.2 Integration Approaches for CPO       51
    • 1.11.3 TSMC's Role in Heterogeneous Integration 52
  • 1.15     Overview of Interconnection Techniques in Semiconductor Packaging 52
    • 1.15.1 Wire Bonding 53
    • 1.15.2 Flip-Chip Bumping     53
    • 1.15.3 Micro-Bumping            53
    • 1.15.4 Through-Silicon Via (TSV)       53
    • 1.15.5 Hybrid Bonding            53
    • 1.15.6 Redistribution Layer (RDL)    54
  • 1.16     Key CPO Applications: Network Switch and Computing Optical I/O         54
    • 1.16.1 Scale-Out Network Switching            54
    • 1.16.2 Scale-Up Computing Optical I/O      55
  • 1.17     EIC/PIC Integration by Advanced Interconnect Techniques            56
    • 1.17.1 Integration Requirements      56
  • 1.18     2D to 3D EIC/PIC Integration Options            57
    • 1.18.1 2D Integration Architecture   57
    • 1.18.2 2.5D Integration Architecture              58
    • 1.18.3 3D Integration Architecture   58
  • 1.19     Benchmark of Different Packaging Technologies for EIC/PIC         63
  • 1.20     Examples of Packaging a 3D Optical Engine with an IC      64
    • 1.20.1 Configuration 1: EIC-on-PIC with Micro-Bumps     64
    • 1.20.2 Configuration 2: PIC-on-EIC with Through-Silicon Vias     64
    • 1.20.3 Configuration 3: 3D SoIC with Hybrid Bonding        64
  • 1.21     Types of CPO + XPU/Switch ASIC Packaging Structures    65
    • 1.21.1 Type I: Optical Engines on Package Periphery          65
    • 1.21.2 Type II: Optical Engines Co-Located with ASIC on Interposer        65
    • 1.21.3 Type III: 3D Stacked Optical Engines              66
  • 1.22     Challenges and Future Potential of CPO Technology           67
    • 1.22.1 Technical Challenges               67
    • 1.22.2 Commercial Challenges        67
      • 1.22.2.1            Future Potential           67
  • 1.23     NVIDIA vs. Broadcom: Strategic Comparison in AI Infrastructure and CPO         68
    • 1.23.1 NVIDIA's CPO Strategy: Vertical Integration               68
    • 1.23.2 Broadcom's CPO Strategy: Open Ecosystem           69
    • 1.23.3 Competitive Dynamics           69
    • 1.23.4 CPO Product Benchmark: NVIDIA vs. Broadcom   70
    • 1.23.5 NVIDIA and Broadcom: Divergent CPO Ecosystems           70
  • 1.24     Current AI System Architecture          71
    • 1.24.1 NVIDIA DGX/HGX Architecture           71
  • 1.25     Future AI Architecture              72
  • 1.26     Market Forecast           72
    • 1.26.1 Server Boards, CPUs, and GPUs/Accelerators         72
    • 1.26.2 Optical I/O for AI Interconnect CPO Forecast (Units Shipped)      73
    • 1.26.3 Optical I/O for AI Interconnect CPO Forecast (Revenue/Market Size)      73
    • 1.26.4 CPO Network Switches for AI Accelerators Forecast (Units Shipped)      74
    • 1.26.5 CPO Network Switches for AI Accelerators Forecast (Market Size and Revenue)             75
    • 1.26.6 Total CPO Market Overview  75
    • 1.26.7 Total CPO by Different EIC/PIC Integration Technology (Unit Shipments)              76
    • 1.26.8 System Integration of Network Switches by Packaging Technologies       77
    • 1.26.9 System Integration of Optical I/O Forecast by Packaging Technologies  77
  • 1.27     Co-packaged optics (CPO) industrial ecosystem  77
    • 1.27.1 PIC Design Segment  78
    • 1.27.2 ASIC and xPU Design Segment           78
    • 1.27.3 Laser Sources Segment          80
    • 1.27.4 SOI Wafer and Epi-Wafer Segment  80
    • 1.27.5 EIC, Retimers, SerDes, and PHY Segment  81
    • 1.27.6 Connectors and Fibers Segment      82
    • 1.27.7 Foundries Segment    82
    • 1.27.8 Packaging, Assembling, and Testing Segment         83
    • 1.27.9 System and Equipment Segment     84
  • 1.27.10              End Customers (Hyperscalers) Segment    84
  • 1.27.11              Ecosystem Interdependencies and Strategic Implications              85

 

2             CHALLENGES AND SOLUTIONS FOR FUTURE AI SYSTEMS            88

  • 2.1        The Rise and Challenges of Large Language Models (LLMs)           88
    • 2.1.1    The Explosive Growth of AI and Generative AI           88
      • 2.1.1.1 Historical Context and Acceleration               88
      • 2.1.1.2 Compute Demand Scaling   88
      • 2.1.1.3 Generative AI Market Expansion       88
    • 2.1.2    Modern High-Performance AI Data Centre Requirements               90
      • 2.1.2.1 Compute Density Requirements      90
      • 2.1.2.2 Network Topology Requirements      90
      • 2.1.2.3 Availability and Reliability Requirements    90
    • 2.1.3    NVIDIA's State-of-the-Art AI Systems             91
      • 2.1.3.1 DGX H100 and HGX H100     91
    • 2.1.4    Switches: Key Components in Modern Data Centres          93
      • 2.1.4.1 Switch Hierarchy in AI Data Centres               93
  • 2.2        Scale-Up, Scale-Out, and Scale-Across Networks               94
    • 2.2.1    Scale-Up Networks: GPU-to-GPU Interconnects   94
      • 2.2.1.1 NVIDIA NVLink Implementation        94
      • 2.2.1.2 CPO Value Proposition for Scale-Up               95
    • 2.2.2    Scale-Out Networks: Rack-to-Rack Communications      96
      • 2.2.2.1 Ethernet-Based Scale-Out    96
      • 2.2.2.2 InfiniBand for AI            96
      • 2.2.2.3 CPO Value Proposition for Scale-Out            96
    • 2.2.3    Scale-Up, Scale-Out, and Scale-Across Comparison        97
  • 2.3        Challenges in Network Switch Interconnects for High-End Data Centres              98
    • 2.3.1    Roadmap of Interconnect Technology for Network Switches in High-End Data Centres              98
      • 2.3.1.1 Technology Generations         98
    • 2.3.2    SerDes Bottleneck in High-Bandwidth Systems     100
      • 2.3.2.1 SerDes Function          100
      • 2.3.2.2 Channel Loss Challenges      100
    • 2.3.3    Solutions to SerDes Bottlenecks in High-Bandwidth Systems      101
      • 2.3.3.1 Linear-Drive Electronics         101
      • 2.3.3.2 Near-Package Optics                101
      • 2.3.3.3 Co-Packaged Optics 101
    • 2.3.4    Pluggable Optics: Current Bottlenecks and Limitations   102
      • 2.3.4.1 Form Factor Constraints        102
      • 2.3.4.2 Electrical Interface Limitations          102
      • 2.3.4.3 Thermal Management Challenges   102
      • 2.3.4.4 Serviceability Trade-offs        102
    • 2.3.5    On-Board Optics (OBO)          103
    • 2.3.6    Co-Packaged Optics (CPO)  104
      • 2.3.6.1 CPO Architecture        104
      • 2.3.6.2 Key Enabling Technologies    105
      • 2.3.6.3 Performance Benefits              105
      • 2.3.6.4 Implementation Challenges 105
    • 2.3.7    Transmission Losses in Pluggable Optical Transceiver Connections        106
      • 2.3.7.1 Total Path Loss             106
    • 2.3.8    Pluggable Optics vs. CPO      107
    • 2.3.9    Design Decisions for CPO Compared to Pluggables           108
    • 2.3.10 Advancements in Switch IC Bandwidth and the Need for CPO Technology          109
      • 2.3.10.1            Bandwidth Scaling Trajectory              109
      • 2.3.10.2            Physical Constraints at Scale              109
    • 2.3.11 L2 Frontside Network Architecture Diagram: CPO vs. Non-CPO 110
  • 2.4        Challenges in Compute Switch Interconnects (Optical I/O) for High-End Data Centres              111
    • 2.4.1    Number of Copper Wires in Current AI System Interconnects       111
      • 2.4.1.1 NVLink Copper Cable Count               111
      • 2.4.1.2 SuperPOD Cable Complexity              111
    • 2.4.2    Limitations of Current Copper Systems in AI            112
    • 2.4.3    NVIDIA's Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems          113
      • 2.4.3.1 Current Generation: Copper-Centric             114
      • 2.4.3.2 Transition Generation: Hybrid Approach     114
      • 2.4.3.3 Future Generation: Optical-First       114
      • 2.4.3.4 Strategic Implications              114
    • 2.4.4    Copper vs. Optical for High-Bandwidth Systems: Benchmark      114
    • 2.4.5    Migration from Copper to Optical Interconnects for High-End AI Systems            115
    • 2.4.6    Current AI System Architecture          116
    • 2.4.7    L1 Backside Compute Architecture with Copper Systems              117
    • 2.4.8    L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO)    118
    • 2.4.9    Opportunities for Swapping Copper to Optical       118
  • 2.5        Future AI Systems in High-End Data Centres            119
    • 2.5.1    Power Efficiency Comparison: CPO vs. Pluggable Optics vs. Copper Interconnects      119
    • 2.5.1.1 Power Consumption Breakdown      119
    • 2.5.2    Latency of 60cm Data Transmission Technology Benchmark        121
    • 2.5.3    Future AI Architecture (Short to Mid-Term) 121
    • 2.5.4    Future AI Architecture (Long-Term)  123

 

3             INTRODUCTION TO CO-PACKAGED OPTICS (CPO)             126

  • 3.1        Photonic Integrated Circuits (PICs) Key Concepts 126
    • 3.1.1    What are Photonic Integrated Circuits (PICs)?         126
      • 3.1.1.1 Fundamental Definition         126
      • 3.1.1.2 Material Platforms      126
      • 3.1.1.3 Integration Levels        126
    • 3.1.2    PICs vs. Silicon Photonics: What are the Differences?       128
      • 3.1.2.1 Silicon Photonics: A Specific Implementation         128
      • 3.1.2.2 Why Silicon Photonics Dominates CPO       128
    • 3.1.3    PIC Architecture           129
      • 3.1.3.1 Transmit Path Architecture    129
      • 3.1.3.2 Receive Path Architecture     130
      • 3.1.3.3 Supporting Functions               130
    • 3.1.4    Advantages and Challenges of PICs               131
  • 3.2        Optical Engine (OE)   132
    • 3.2.1    What is an Optical Engine?   132
      • 3.2.1.1 Optical Engine Composition               132
      • 3.2.1.2 Optical Engine vs. Pluggable Transceiver    133
    • 3.2.2    How an Optical Engine Works            133
      • 3.2.2.1 Transmit Path Operation         133
      • 3.2.2.2 Receive Path Operation          134
      • 3.2.2.3 Critical Performance Parameters     134
    • 3.2.3    Optical Power Supplies           134
      • 3.2.3.1 Why External Laser Sources?              134
      • 3.2.3.2 External Laser Source Architectures              135
      • 3.2.3.3 Optical Power Delivery            135
  • 3.3        Co-Packaged Optics 136
    • 3.3.1    Three Key Concepts in Co-Packaged Optics (CPO)              136
      • 3.3.1.1 Concept 1: Proximity Integration       136
      • 3.3.1.2 Concept 2: Functional Partitioning 136
      • 3.3.1.3 Concept 3: Coherent Ecosystem Development      136
    • 3.3.2    Key Technology Building Blocks for CPO      137
      • 3.3.2.1 Silicon Photonics PIC               137
      • 3.3.2.2 Electronic IC (EIC)      138
      • 3.3.2.3 EIC-PIC Integration    138
      • 3.3.2.4 Fibre Array Units (FAUs)          138
      • 3.3.2.5 External Laser Source              138
      • 3.3.2.6 Advanced Packaging Platform            138
    • 3.3.3    Benefits of CPO: Latency Reduction              140
      • 3.3.3.1 Sources of Latency in Optical Interconnects            140
      • 3.3.3.2 CPO Latency Advantages      141
    • 3.3.4    Benefits of CPO: Power Consumption Reduction  141
      • 3.3.4.1 Power Consumption Breakdown      141
      • 3.3.4.2 Why CPO Consumes Less Power     142
    • 3.3.5    Benefits of CPO: Data Rate Improvements 142
      • 3.3.5.1 Pluggable Scaling Limitations             143
      • 3.3.5.2 CPO Scaling Advantages       143
      • 3.3.5.3 Data Rate Scaling Roadmap               143
    • 3.3.6    Overview of Value Proposition of CPO          143
      • 3.3.6.1 Value for Hyperscale Data Centre Operators            144
      • 3.3.6.2 Value for Network Equipment Vendors         144
      • 3.3.6.3 Value for the Technology Ecosystem              144
    • 3.3.7    Future Challenges in CPO     144
      • 3.3.7.1 Manufacturing and Yield Challenges             144
      • 3.3.7.2 Thermal Management Challenges   145
      • 3.3.7.3 Serviceability and Reliability Challenges    145
      • 3.3.7.4 Ecosystem and Standardisation Challenges            145
      • 3.3.7.5 Cost Challenges          145
  • 3.4        CPO Standards            146
    • 3.4.1    OIF Co-Packaging Framework            147
    • 3.4.2    OIF Standards for 1.6T and 3.2T CPO Module          147
    • 3.4.3    External Laser Small Form Pluggable (ELSFP) Implementation Agreement          148
    • 3.4.4    Telemetry and Management 148
    • 3.4.5    OIF's CEI-112G XSR / XSR+ PAM4     149
    • 3.4.6    UCIe Standard and Its Relationship to CPO              150
    • 3.4.7    The CPO Standards Process in China           150

 

4             PACKAGING FOR CO-PACKAGED OPTICS (CPO)  152

  • 4.1        Introduction to CPO Packaging         152
    • 4.1.1    Key Components to be Packaged in an Optical Transceiver           152
      • 4.1.1.1 Photonic Integrated Circuit (PIC)      152
      • 4.1.1.2 Electronic Integrated Circuit (EIC)   152
      • 4.1.1.3 Laser Source Interface            152
      • 4.1.1.4 Fibre Array Unit (FAU)               152
      • 4.1.1.5 Host ASIC Interface   153
    • 4.1.2    Heterogeneous Integration and Co-Packaged Photonics 153
      • 4.1.2.1 Why Heterogeneous Integration for CPO?  153
      • 4.1.2.2 Heterogeneous Integration Approaches for CPO   154
      • 4.1.2.3 Integration Hierarchy for CPO             154
    • 4.1.3    CPO for Network Switch: Packaging Concept          154
      • 4.1.3.1 Switch Architecture with CPO            154
      • 4.1.3.2 Package Configuration Options         155
      • 4.1.3.3 Packaging Requirements for Switch CPO    155
    • 4.1.4    1.6 Tbps Co-Packaged Optics for Network Switch                155
      • 4.1.4.1 Integration Approach                156
    • 4.1.5    CPO as Optical I/O for XPUs: Packaging Concept 157
      • 4.1.5.1 The Scale-Up Interconnect Challenge          157
      • 4.1.5.2 XPU-CPO Packaging Concept             157
      • 4.1.5.3 Implementation Approaches              157
      • 4.1.5.4 NVIDIA's Approach to XPU Optical I/O          161
      • 4.1.5.5 Packaging Implications for XPU Optical I/O               161
      • 4.1.5.6 System Architecture Evolution           161
    • 4.1.6    CPO Integration for Compute Silicon             162
      • 4.1.6.1 System Configuration              162
      • 4.1.6.2 Integration Architecture          163
      • 4.1.6.3 Thermal Partitioning 163
      • 4.1.6.4 Enabled Architectures             163
    • 4.1.7    Overview of CPO Packaging Technologies  163
  • 4.2        Overview and Development Roadmap of 2.5D and 3D Advanced Semiconductor Packaging Technologies  165
    • 4.2.1    Evolution Roadmap of Semiconductor Packaging 165
    • 4.2.2    Semiconductor Packaging Overview             166
    • 4.2.3    Key Metrics for Advanced Semiconductor Packaging Performance          169
    • 4.2.4    Overview of Interconnection Techniques in Semiconductor Packaging 173
    • 4.2.5    Overview of 2.5D Packaging Structure          176
    • 4.2.6    2.5D Package Components 176
    • 4.2.7    Benefits for CPO          176
    • 4.2.8    Challenges for CPO   176
  • 4.3        2.5D Silicon-Based Packaging Technologies            177
    • 4.3.1    2.5D Packaging Involving Silicon as Interconnect  177
    • 4.3.2    Silicon Interposer Technology             177
    • 4.3.3    Silicon Bridge Technology      177
    • 4.3.4    CPO Implications        178
    • 4.3.5    Through-Silicon Via (TSV): Current State and Future            182
      • 4.3.5.1 TSV Fabrication Process         182
      • 4.3.5.2 TSV Technology Generations               183
      • 4.3.5.3 TSV Challenges for CPO         183
      • 4.3.5.4 Future TSV Development        184
    • 4.3.6    Development Trends for 2.5D Silicon-Based Packaging   186
      • 4.3.6.1 Interposer Size Scaling            186
      • 4.3.6.2 Routing Density Advancement           186
      • 4.3.6.3 Cost Reduction Initiatives     186
      • 4.3.6.4 Integration with Advanced Features                186
    • 4.3.7    Silicon Interposer vs. Silicon Bridge Benchmark    190
    • 4.3.7.1 Implications for CPO 191
  • 4.4        2.5D Organic-Based Packaging Technologies          192
    • 4.4.1    2.5D Packaging: High-Density Fan-Out (FO) Packaging    192
      • 4.4.1.1 Fan-Out Technology Concept             192
      • 4.4.1.2 High-Density Fan-Out Variants          192
      • 4.4.1.3 Advantages for CPO  192
      • 4.4.1.4 Challenges for CPO   192
    • 4.4.2    Redistribution Layer (RDL)    193
      • 4.4.2.1 RDL Fabrication Process        193
      • 4.4.2.2 RDL Design Considerations for CPO              193
    • 4.4.3    Electronic Interconnects: SiO2 vs. Organic Dielectric         194
    • 4.4.4    Panel Level Fab-Out  196
      • 4.4.4.1 Panel-Level Processing           196
      • 4.4.4.2 Advantages for CPO  196
      • 4.4.4.3 Challenges for CPO   196
    • 4.4.5    Wafer Level Fan-Out 197
      • 4.4.5.1 Wafer-Level Processing          197
      • 4.4.5.2 Advantages for WLFO               197
      • 4.4.5.3 Challenges for WLFO                198
    • 4.4.6    Wafer-Level Fan-Out vs. Panel-Level Fan-Out         198
      • 4.4.6.1 Selection Criteria for CPO     199
    • 4.4.7    Key Trends in Fan-Out Packaging     199
    • 4.4.8    Challenges in Future Fan-Out Processes    201
      • 4.4.8.1 Die Shift and Placement Accuracy   201
      • 4.4.8.2 Warpage Control         201
      • 4.4.8.3 Yield and Cost               201
      • 4.4.8.4 High-Frequency Performance             202
  • 4.5        2.5D Glass-Based Packaging Technologies               204
    • 4.5.1    Roles of Glass in Semiconductor Packaging            204
      • 4.5.1.1 Glass Properties Relevant to Packaging      204
      • 4.5.1.2 Applications in Packaging     205
      • 4.5.1.3 Glass Core as Interposer for Advanced Semiconductor Packaging          206
    • 4.5.2    Overcoming Limitations of Silicon Interposers with Glass              208
      • 4.5.2.1 Size Limitation              208
      • 4.5.2.2 Optical Opacity            208
      • 4.5.2.3 Dielectric Loss              208
      • 4.5.2.4 Cost Structure               208
      • 4.5.2.5 Remaining Silicon Advantages           208
    • 4.5.3    Glass vs. Molding Compound             209
      • 4.5.3.1 Implications for CPO 210
    • 4.5.4    Glass Core (Interposer) Package: Process Flow     210
    • 4.5.5    Challenges of Glass Packaging         212
      • 4.5.5.1 Handling and Breakage           212
      • 4.5.5.2 Via Formation and Metallisation       212
      • 4.5.5.3 Thermal Conductivity               212
      • 4.5.5.4 RDL Adhesion                212
      • 4.5.5.5 Warpage Control         212
  • 4.6        3D Advanced Semiconductor Packaging Technologies     218
    • 4.6.1    Evolution of Bumping Technologies 218
      • 4.6.1.1 Solder Bumps (C4)     218
      • 4.6.1.2 Copper Pillar Bumps 218
      • 4.6.1.3 Micro-Bumps 218
      • 4.6.1.4 Hybrid Bonding (Bumpless) 218
    • 4.6.2    Challenges in Scaling Bumps             218
      • 4.6.2.1 Mechanical Challenges          218
      • 4.6.2.2 Electrical Challenges               219
      • 4.6.2.3 Manufacturing Challenges   219
      • 4.6.2.4 Implications for CPO 219
    • 4.6.3    Micro-Bump for Advanced Semiconductor Packaging      222
      • 4.6.3.1 Micro-Bump Structure             222
    • 4.6.4    Bumpless Cu-Cu Hybrid Bonding    222
      • 4.6.4.1 Hybrid Bonding Concept        222
      • 4.6.4.2 Process Fundamentals           222
      • 4.6.4.3 Key Characteristics   222
      • 4.6.4.4 Benefits for CPO          223
    • 4.6.5    Three Ways of Cu-Cu Hybrid Bonding: Benchmark              223
      • 4.6.5.1 Die-to-Die (D2D)         223
      • 4.6.5.2 Die-to-Wafer (D2W)  223
      • 4.6.5.3 Wafer-to-Wafer (W2W)            223
    • 4.6.6    Challenges in Cu-Cu Hybrid Bonding Manufacturing Process      225
  • 4.7        CPO Packaging: EIC and PIC Integration      229
    • 4.7.1    EIC/PIC Integration by Conventional Interconnect Techniques    229
      • 4.7.1.1 Wire Bond Integration               229
      • 4.7.1.2 Flip-Chip Integration (2D)      230
    • 4.7.2    EIC/PIC Integration by Emerging Interconnect Techniques              232
      • 4.7.2.1 2.5D Interposer Integration   232
      • 4.7.2.2 3D Micro-Bump Stacking       232
      • 4.7.2.3 3D Hybrid Bonding     232
    • 4.7.3    2D to 3D EIC/PIC Integration Options            234
      • 4.7.3.1 Technology Transition Drivers             236
      • 4.7.3.2 2D to 3D Integration Evolution            237
    • 4.7.4    Integration Roadmap by CPO Segment        238
    • 4.7.5    Benchmarking of Different Packaging Technologies for EIC/PIC  239
    • 4.7.6    Pros and Cons of 2D Integration of EIC/PIC               239
    • 4.7.7    Pros and Cons of 2.5D Integration of EIC/PIC           240
    • 4.7.8    Pros and Cons of 3D Hybrid Integration of EIC/PIC               241
    • 4.7.9    Pros and Cons of 3D Monolithic Integration of EIC/PIC      242
  • 4.8        TSV for EIC/PIC Integration   243
    • 4.8.1    TSV for EIC/PIC Integration in CPO  243
      • 4.8.1.1 TSV Configurations for EIC/PIC          243
      • 4.8.1.2 Design Considerations            243
    • 4.8.2    Benefits of TSV for PIC/EIC Integration          244
    • 4.8.3    Cisco Packaging Architectures of Optical Engine Over Generations         245
    • 4.8.4    Cisco: 2.5D Chip-on-Chip (CoC) Packaging Architecture for EIC/PIC Integration            246
      • 4.8.4.1 Architecture Description        246
      • 4.8.4.2 Manufacturing Considerations          246
    • 4.8.5    Cisco: 3D TSV for PIC/EIC Integration            247
      • 4.8.5.1 Architecture Description        247
      • 4.8.5.2 Benefits of TSV Integration    247
      • 4.8.5.3 Manufacturing Considerations          247
    • 4.8.6    Key TSV Fabrication Steps and Challenges in CPO               247
      • 4.8.6.1 Fabrication Process Flow      248
    • 4.8.7    Packaging Options for Silicon Photonics     249
    • 4.8.8    Pros and Cons of 2.5D Si Interposer for EIC/PIC Integration           249
  • 4.9        Fan-Out for EIC/PIC Integration         250
    • 4.9.1    ASE's Proposed Fan-Out Solution for CPO Packaging        250
      • 4.9.1.1 ASE Fan-Out CPO Concept  250
    • 4.9.2    FOPOP from ASE: Process    251
    • 4.9.3    Analysis of FOPOP vs. Wire Bond Packaging for CPO          252
    • 4.9.4    Optical Packaging Process Considerations for Silicon Photonics - ASE  253
    • 4.9.5    SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO        254
    • 4.9.6    Process Flow of Integrating PIC and EIC in a FOEB Structure         255
    • 4.9.7    Process Challenges in Packaging Optical Engines                256
    • 4.9.8    Challenges of Using Fan-Out for EIC/PIC Integration          256
  • 4.10     Glass-Based CPO Packaging Technologies               257
    • 4.10.1 Glass-Based Co-Packaged Optics  257
      • 4.10.1.1            Corning's Glass CPO Vision 257
    • 4.10.2 Glass CPO Package Architecture      258
    • 4.10.3 Glass-Based CPO Process Development    259
      • 4.10.3.1            Corning's 102.4 Tb/s Test Vehicle Demonstration 260
    • 4.10.4 3D Heterogeneous Integration of EIC/PIC on a Glass Interposer 260
      • 4.10.4.1            Architecture Rationale             260
      • 4.10.4.2            Package Architecture                261
      • 4.10.4.3            Process Flow  261
      • 4.10.4.4            Representative Switch Module Example     262
      • 4.10.4.5            Market Trajectory        263
  • 4.11     Hybrid Bonding for EIC/PIC Integration         263
    • 4.11.1 TSMC: Integrated HPC Technology Platform for AI 263
    • 4.11.2 iOIS: Integrated Optical Interconnection System from TSMC        264
    • 4.11.3 Combining EIC and PIC with 3D SoIC Bond               265
    • 4.11.4 Roadmap of Bond Pitch Scaling        266
  • 4.12     System Integration of Optical Engine and ASIC/XPU            267
    • 4.12.1 Co-Packaging vs. Co-Packaged Optics (CPO)         267
    • 4.12.2 Three Types of CPO + XPU/Switch ASIC Packaging Structures      268
      • 4.12.2.1            Type 1: 2D/2.5D Peripheral Integration          268
      • 4.12.2.2            Type 2: 2.5D with Embedded Bridge               268
      • 4.12.2.3            Type 3: 3D Stacked Integration           268
  • 4.13     Future 3D-CPO Structure       269
    • 4.13.1 Future 3D-CPO Architecture Vision 269
    • 4.13.2 NVIDIA's 3D Integration of SoC, HBM, EIC, and PIC on Co-Packaged Substrates             273
      • 4.13.2.1.1        Architecture Overview             273
      • 4.13.2.1.2        Integration Approach                273
      • 4.13.2.1.3        Key Innovations            273
  • 4.14     Optical Alignment and Laser Integration     274
    • 4.14.1 How CPO is Built and the Bottleneck             274
    • 4.14.2 The fibre attach bottleneck   274
    • 4.14.3 Interface Between Coupler and FAU              275
    • 4.14.4 Grating vs. Edge Couplers: Challenges in High-Density Optical I/O for Silicon Photonics          276
    • 4.14.5 Challenges in High-Density Optical I/O for Silicon Photonics       277
  • 4.15     Fiber Array Unit (FAU)               278
    • 4.15.1 Optical Alignment Challenges and Solutions           278
    • 4.15.2 Two Alignment Approaches 279
    • 4.15.3 Reducing Optical Fiber Packaging Complexity        280
    • 4.15.4 Key Technical Challenges      280
      • 4.15.4.1            The Size Mismatch Between Silicon Waveguides and Planar Optical Fibers        280
    • 4.15.5 Fiber Attach Methods               281
    • 4.15.6 Key Players in FAU for CPO   283
    • 4.15.7 Benchmark of Optical Fiber Alignment Structure Variations          283
    • 4.15.8 Suppliers of Other Optical Components in CPO    286
  • 4.16     Suppliers of Other Optical Components in CPO    286
  • 4.17     Laser Integration          291
    • 4.17.1 On-Chip Light Source Integration Methods                291
    • 4.17.2 External Lasers for CPO          292
    • 4.17.3 Laser Attach Technology Benchmark            296
    • 4.17.4 Benchmark of Different Laser Integration Technologies    297

 

5             CO-PACKAGED OPTICS MARKET ANALYSIS               299

  • 5.1        CPO Market Definition and Scope    299
  • 5.2        CPO Market Size and Growth Projections   299
  • 5.3        Switch CPO Market Analysis               300
    • 5.3.1    Market Overview and Drivers               300
    • 5.3.2    Deployment Timeline and Adoption Phases             300
    • 5.3.3    Volume Projections and Market Sizing          300
    • 5.3.4    Market Concentration and Regional Distribution   301
    • 5.3.5    Pricing Trajectory and Cost Dynamics          302
  • 5.4        XPU Optical I/O Market Analysis       302
    • 5.4.1    Market Drivers and Value Proposition           302
    • 5.4.2    Adoption Timeline and Platform Evolution 303
    • 5.4.3    Volume and Revenue Projections     303
    • 5.4.4    Market Segmentation by Platform    304
    • 5.4.5    Technology Requirements and Differentiation         304
  • 5.5        CPO Pricing and Cost Analysis          305
    • 5.5.1    Current Pricing Landscape   305
    • 5.5.2    Cost Trajectory and Reduction Drivers          305
    • 5.5.3    Cost Parity Timeline and Dynamics 306
    • 5.5.4    Pricing Strategy Implications               307
  • 5.6        Regional Market Dynamics   307
    • 5.6.1    North America              307
    • 5.6.2    Asia-Pacific    308
    • 5.6.3    Europe                309
    • 5.6.4    Rest of World 309
  • 5.7        Total Addressable Market Analysis  310
    • 5.7.1    Core TAM Segments  310
    • 5.7.2    Serviceable Addressable Market (SAM)       311
  • 5.8        Market Forecast by Component        312
  • 5.9        Market Forecast by Technology Generation               313
    • 5.9.1    Optical Engine Bandwidth Evolution              313
    • 5.9.2    Generation Lifecycle Analysis            314
  • 5.10     Market Restraints and Barriers           314
    • 5.10.1 Manufacturing Yield and Cost            314
    • 5.10.2 Serviceability and Field Replacement Concerns    315
    • 5.10.3 Standards Maturity and Interoperability       316
    • 5.10.4 Supply Chain Capacity Constraints               317
    • 5.10.5 Competitive Alternatives        318
  • 5.11     Adoption Curve Analysis        319
    • 5.11.1 Technology Adoption Framework     319
      • 5.11.1.1            Innovators (2024-2026)          319
      • 5.11.1.2            Early Adopters (2026-2028) 319
      • 5.11.1.3            Early Majority (2028-2031)   320
      • 5.11.1.4            Late Majority (2031-2034)     320
      • 5.11.1.5            Laggards (2034+)        321
    • 5.11.2 Segment-Specific Adoption Curves                321
  • 5.12     Adoption Accelerators and Inhibitors            322
    • 5.12.1 Adoption Curve Implications               323
  • 5.13     Competitive Landscape Evolution   323
    • 5.13.1 Current Competitive Positioning      323
    • 5.13.2 Integrated Device Manufacturers (IDMs)     323
    • 5.13.3 Silicon Photonics Specialists              323
    • 5.13.4 Foundry/OSAT Providers         324
    • 5.13.5 System Vendors           324
    • 5.13.6 Laser Suppliers             324
    • 5.13.7 Competitive Dynamics and Market Structure Evolution    325
      • 5.13.7.1            Near-Term Dynamics (2025-2028)  325
        • 5.13.7.1.1        Expected Evolution (2028)    325
      • 5.13.7.2            Mid-Term Dynamics (2028-2032)     325
        • 5.13.7.2.1        Expected Evolution (2032)    326
      • 5.13.7.3            Long-Term Dynamics (2032-2036)  326
        • 5.13.7.3.1        Expected Evolution (2036)    326
    • 5.13.8 Vertical Integration Trends    327
      • 5.13.8.1            Integration Strategy Framework         327
        • 5.13.8.1.1        Full Vertical Integration (Broadcom, Intel Model)   327
        • 5.13.8.1.2        Partial Integration (Cisco, NVIDIA Model)    327
        • 5.13.8.1.3        Fabless/Assembly-Light (Ayar Labs, Ranovus Model)         328
        • 5.13.8.1.4        Platform Provider (TSMC Model)       328
      • 5.13.8.2            Strategic Implications of Integration Trends              329
    • 5.13.9 Recent Developments — Q1 2026 Update 330
  • 5.14     Scenario Analysis       330
    • 5.14.1 Scenario Framework 330
    • 5.14.2 Scenario Definitions 331
    • 5.14.3 Bull Case Scenario     331
    • 5.14.4 Base Case Scenario  332
    • 5.14.5 Bear Case Scenario   333
    • 5.14.6 Scenario Comparison and Key Variables    334

 

6             GLOBAL MARKET TRENDS IN DATACOM     336

  • 6.1        Introduction to DATACOM Market Dynamics            336
    • 6.1.1    Overview of the Data Communications Market       336
      • 6.1.1.1 Market Definition and Scope               336
      • 6.1.1.2 Market Size and Growth          336
    • 6.1.2    Key Market Drivers      336
      • 6.1.2.1 Artificial Intelligence and Machine Learning             336
      • 6.1.2.2 Cloud Computing Growth     337
      • 6.1.2.3 Data Growth   337
      • 6.1.2.4 Power and Sustainability Pressures                337
  • 6.2        Application Trends     338
    • 6.2.1    AI and Machine Learning Workload Growth               338
      • 6.2.1.1 The AI Training Revolution     338
      • 6.2.1.2 Training Cluster Architecture Evolution        338
      • 6.2.1.3 AI Inference Deployment        338
      • 6.2.1.4 Market Quantification              339
      • 6.2.1.5 Implications for CPO 339
    • 6.2.2    Hyperscale Data Centre Expansion 339
      • 6.2.2.1 Defining Hyperscale  339
    • 6.2.3    Global Hyperscale Capacity                339
    • 6.2.4    Regional Distribution                340
    • 6.2.5    Hyperscaler Investment Trends         340
      • 6.2.5.1 Capital expenditure acceleration     340
      • 6.2.5.2 AI-Specific Infrastructure       340
      • 6.2.5.3 Implications for CPO 340
    • 6.2.6    Edge Computing and Distributed AI                340
      • 6.2.6.1 Market Growth              341
    • 6.2.7    Edge AI Applications 341
    • 6.2.8    Edge Network Architecture   341
  • 6.3        Technology Trends      342
    • 6.3.1    Technology Trends Overview               342
      • 6.3.1.1 Key Technology Vectors          342
      • 6.3.1.2 Technology Interdependencies          342
    • 6.3.2    Technology Trends: Packaging           343
    • 6.3.3    Universal Chiplet Interconnect Express (UCIe)       344
    • 6.3.4    Laser Sources for CPO            345
    • 6.3.5    External vs. Integrated Laser                345

 

7             MARKET OUTLOOK    347

  • 7.1        Hybrid Pluggable-to-CPO Transition, 2026–2030  347
  • 7.2        Scale-Out Outlook     347
    • 7.2.1    Scale-Out CPO Market Evolution     347
      • 7.2.1.1 Scale-Out Market Drivers       348
      • 7.2.1.2 Market Evolution Phases        348
      • 7.2.1.3 Scale-Out CPO Market Forecast       348
    • 7.2.2    Scale-Out Technology Roadmap      349
      • 7.2.2.1 Technology Generation Evolution     349
      • 7.2.2.2 Technology Enablers by Generation                350
    • 7.2.3    Scale-Out Key Players and Competitive Landscape            350
  • 7.3        Scale-Up Outlook       351
    • 7.3.1    Scale-Up CPO Market Evolution       351
    • 7.3.2    Copper to Optical Transition               351
    • 7.3.3    Optical I/O Solution   351
    • 7.3.4    Scale-Up CPO Market Forecast         352
    • 7.3.5    Market Evolution Phases        352
    • 7.3.6    Scale-Up Technology Roadmap        353
      • 7.3.6.1 NVIDIA Optical I/O Evolution               353
      • 7.3.6.2 AMD Optical I/O Evolution    354
      • 7.3.6.3 Custom Silicon Optical I/O   354
    • 7.3.7    Scale-Up Key Players and Competitive Landscape              355
    • 7.3.7.1 Competitive Landscape Overview   355
  • 7.4        High-Density Connectors      356
    • 7.4.1    High-Density Connectors vs. CPO   356
      • 7.4.1.1 Scenario 1: Connectors Enable Extended Pluggable (Low CPO Impact) 356
      • 7.4.1.2 Scenario 2: Connectors Complement CPO (Moderate Impact)   356
      • 7.4.1.3 Scenario 3: Connectors Enable "Near-Packaged" Optics (Moderate CPO Impact)         356
      • 7.4.1.4 Scenario 4: Connector Development Delays (Positive CPO Impact)        357
  • 7.5        Emerging Supply Chain Dynamics   361
    • 7.5.1    Geographic Concentration in CPO Supply Chains                361
  • 7.6        Third-Party Suppliers and Systems Integrators        363
    • 7.6.1    Multi-Tier Supply Chain Architecture              363
      • 7.6.1.1 Tier 1: Silicon Photonics Platform     364
      • 7.6.1.2 Tier 2: CPO Assembly (OSAT)              364
      • 7.6.1.3 Tier 3: Fiber Array Unit (FAU) Suppliers          365
      • 7.6.1.4 Tier 4: External Laser Source (ELS) Suppliers            365
      • 7.6.1.5 Tier 5: Optical Fiber Supply   365
      • 7.6.1.6 Tier 6: Optical Sub-Assembly Integration    366
    • 7.6.2    Strategic Implications for Supply Chain Participants          366

 

8             COMPANY PROFILES                367 (63 company profiles)

 

9             APPENDIX        438

  • 9.1        Research Methodology and Data Sources  438

 

10          REFERENCES 439

 

List of Tables

  • Table 1. CPO Market Drivers and Restraints Analysis         37
  • Table 2. Key Data Centre Architecture Challenges Summary        41
  • Table 3. Key Data Centre Architecture Challenges Summary.       44
  • Table 4. Form Factor Evolution and Density Comparison 46
  • Table 5. Optical Transceiver Power Consumption by Generation 47
  • Table 6. Technology Migration Decision Framework             47
  • Table 7. CPO vs. Pluggables Decision Matrix             48
  • Table 8. Semiconductor Packaging Interconnection Techniques Overview          54
  • Table 9. CPO Application Segmentation (Scale-Out vs. Scale-Up)             56
  • Table 10. EIC/PIC Integration Methods Comparison           57
  • Table 11. Integration Technology Selection Criteria              61
  • Table 12. Detailed Technical Comparison: 2D vs 2.5D vs 3D         62
  • Table 13. 3D Integration Sub-Categories Comparison       62
  • Table 14. Packaging Technology Benchmark for EIC/PIC Integration        63
  • Table 15. CPO Technology Challenges and Mitigation Strategies 68
  • Table 16. NVIDIA vs. Broadcom Strategic Positioning Comparison           69
  • Table 17. NVIDIA vs. Broadcom CPO Product Specifications Benchmark             70
  • Table 18. Server Boards, CPUs, and GPU/Accelerator Forecast (2026-2036)     72
  • Table 19. Optical I/O for AI Interconnect CPO — Unit Shipment Forecast (2026–2036)               73
  • Table 20. Optical I/O for AI Interconnect CPO — Revenue Forecast ($M) (2026–2036) 73
  • Table 21. CPO Network Switches — Unit Shipment Forecast (2026–2036)          74
  • Table 22. CPO Network Switches — Optical Engine Revenue Forecast ($M) (2026–2036)         75
  • Table 23. Total CPO Market Size and Revenue (2026–2036)           75
  • Table 24. Total CPO by EIC/PIC Integration Technology — Unit Shipments (2026–2036)             76
  • Table 25. Network Switch CPO Adoption by Packaging Technology           77
  • Table 26. Optical I/O Forecast by Packaging Technology  77
  • Table 27. PIC Design Segment - Key Players and Capabilities       78
  • Table 28. ASIC and xPU Design Segment - Key Players and CPO Integration Strategies                79
  • Table 29. Laser Sources Segment - Key Suppliers and Technologies        80
  • Table 30. SOI Wafer and Epi-Wafer Segment - Substrate Suppliers            81
  • Table 31. EIC, Retimers, SerDes, and PHY Segment - High-Speed Electronics Suppliers           81
  • Table 32. Connectors and Fibers Segment - Optical Infrastructure Suppliers     82
  • Table 33. Foundries Segment - Silicon Photonics and Advanced Packaging Capabilities          83
  • Table 34. Packaging, Assembling, and Testing Segment - OSAT and Test Equipment Providers              83
  • Table 35. System and Equipment Segment - OEMs and ODMs    84
  • Table 36. End Customers (Hyperscalers) Segment - Data Centre Operators and AI Leaders    85
  • Table 37. CPO Industrial Ecosystem Summary - Complete Value Chain Overview         86
  • Table 38. AI Model Parameter and Compute Growth (2018-2030)             89
  • Table 39. Global AI Training Compute Demand Growth     89
  • Table 40. AI Data Centre Requirements by Workload Type               91
  • Table 41. Switch Hierarchy in AI Data Centres          94
  • Table 42. Scale-Up vs. Scale-Out vs. Scale-Across Comparison Matrix 97
  • Table 43. SerDes Bandwidth Limitations and Power Consumption           100
  • Table 44. SerDes Bottleneck Solutions Comparison           101
  • Table 45. Pluggable Optics Architecture and Limitations 102
  • Table 46. Signal Loss Comparison: Pluggable vs. CPO (dB)            107
  • Table 47. Comprehensive Pluggable vs. CPO Comparison             107
  • Table 48. Design Decision Framework for CPO Adoption 108
  • Table 49. L2 Network Architecture Comparison     110
  • Table 50.Copper Wire Count in Current AI Systems             111
  • Table 51. Copper Interconnect Specifications by System 112
  • Table 52. Copper System Limitations Summary     113
  • Table 53. Copper vs. Optical Performance Benchmark     114
  • Table 54. Power Consumption by Interconnect Technology            120
  • Table 55. Power Consumption Component Breakdown: Pluggable vs. CPO (400G)       120
  • Table 56. Latency Benchmark Comparison               121
  • Table 57. PIC Component Overview               127
  • Table 58. PICs vs. Silicon Photonics Comparison 128
  • Table 59. Silicon Photonics vs. Other PIC Platforms: Capability Comparison    129
  • Table 60. PIC Advantages and Challenges Summary          132
  • Table 61. Optical Engine vs. Pluggable Transceiver Comparison 133
  • Table 62. External Laser Source Configurations     135
  • Table 63. CPO Technology Building Blocks 139
  • Table 64. CPO Technology Components and Suppliers     139
  • Table 65. Latency Comparison: Pluggable vs. CPO              141
  • Table 66. Data Rate Scaling: Pluggable vs. CPO      143
  • Table 67. CPO Value Proposition Summary               144
  • Table 68. CPO Technical Challenges and Mitigation Approaches               146
  • Table 69. OIF CPO Standards Development Timeline         146
  • Table 70. OIF CPO Framework Functional Partitioning      147
  • Table 71. OIF CPO Module Specifications by Generation 148
  • Table 72. ELSFP Implementation Agreement Key Specifications 148
  • Table 73. CPO Telemetry and Management Requirements              149
  • Table 74. OIF CEI Specifications for CPO Applications      149
  • Table 75. UCIe Specifications and CPO Relationship         150
  • Table 76. China CPO Standards Landscape              151
  • Table 77. CPO Component Packaging Requirements         153
  • Table 78. Switch CPO Package Specifications (Representative)  155
  • Table 79. 1.6 Tbps Optical Engine Performance      156
  • Table 80. XPU Optical I/O Requirements     157
  • Table 81. Advanced Optical I/O Integration Approaches   159
  • Table 82.Overview of CPO Packaging Technologies             164
  • Table 83. Semiconductor Packaging Technology Landscape         168
  • Table 84. Packaging Technology Comparison for CPO        169
  • Table 85. Advanced Packaging Performance Metrics          170
  • Table 86. Overview of Interconnection Techniques in Semiconductor Packaging            174
  • Table 87.  Interconnection Technique Comparison for CPO           176
  • Table 88. Silicon Interposer vs. Silicon Bridge Comparison            178
  • Table 89. Silicon-Based 2.5D Packaging Options  179
  • Table 90. TSV Specifications by Application              182
  • Table 91. TSV Fabrication Process Steps     182
  • Table 92.TSV Technology Evolution  183
  • Table 93. TSV Challenges for CPO Applications      183
  • Table 94. TSV Technology Evolution.              185
  • Table 95. 2.5D Silicon Packaging Development Trends      186
  • Table 96. Key Development Areas by Technology Node     188
  • Table 97. Interposer Size Evolution for CPO               188
  • Table 98. 2.5D Silicon Packaging Roadmap by Vendor       190
  • Table 99. Roadmap Milestones for CPO Integration             190
  • Table 100. Si Interposer vs. Si Bridge Comparison 190
  • Table 101. RDL Technology Specifications 193
  • Table 102. SiO2 vs. Organic Dielectric Comparison            195
  • Table 103. WLFO vs. PLFO Comparison      198
  • Table 104. Fan-Out Packaging Trends           200
  • Table 105. Fan-Out Process Challenges      202
  • Table 106. Glass Properties vs. Silicon and Organic.           205
  • Table 107. Glass Applications in Semiconductor Packaging         206
  • Table 108. Glass Core Interposer Characteristics 207
  • Table 109. Glass vs. Silicon Interposer Comparison           209
  • Table 110. Glass Interposer Benefits for CPO           209
  • Table 111. Glass vs. Molding Compound Properties            209
  • Table 112. Glass Packaging Challenges and Solutions      214
  • Table 113. Bumping Technology Evolution 218
  • Table 114. Bump Scaling Challenges             220
  • Table 115. Micro-Bump Specifications and Applications 222
  • Table 116. Cu-Cu Hybrid Bonding Methods Comparison 224
  • Table 117. Hybrid Bonding Method Selection for CPO Applications          224
  • Table 118. Hybrid Bonding Manufacturing Challenges       226
  • Table 119. Hybrid Bonding Process Maturity by Pitch          229
  • Table 120. Critical Process Parameters for Hybrid Bonding            229
  • Table 121. Conventional EIC/PIC Integration Methods       230
  • Table 122. Conventional Method Advantages and Limitations Summary              231
  • Table 123. Emerging EIC/PIC Integration Methods 233
  • Table 124. 2D to 3D EIC/PIC Integration Options   235
  • Table 125. Technology Transition Drivers     237
  • Table 126. 2D to 3D Integration Evolution   238
  • Table 127. Integration Roadmap by CPO Segment                238
  • Table 128. EIC/PIC Packaging Technology Benchmark      239
  • Table 129. 2D EIC/PIC Integration Pros and Cons  239
  • Table 130. 2.5D EIC/PIC Integration Pros and Cons             240
  • Table 131. 3D Hybrid EIC/PIC Integration Pros and Cons 241
  • Table 132. 3D Monolithic EIC/PIC Integration Pros and Cons        242
  • Table 133. Benefits of TSV for PIC/EIC Integration 245
  • Table 134. TSV Fabrication Challenges in CPO        248
  • Table 135. Si Photonics Packaging Options Comparison 249
  • Table 136. 2.5D Si Interposer Pros and Cons for EIC/PIC  249
  • Table 137. FOPOP vs. WB Packaging Comparison 252
  • Table 138. Optical Engine Packaging Process Challenges               256
  • Table 139. Fan-Out EIC/PIC Integration Challenges             256
  • Table 140. Bond Pitch Scaling Challenges  267
  • Table 141. Co-Packaging vs. CPO Definition Comparison               267
  • Table 142. Future 3D-CPO Architecture Vision        269
  • Table 143. Architecture Evolution by Component 270
  • Table 144. 3D-CPO Integration Approaches              270
  • Table 145. Future 3D-CPO Packaging Structure Types       271
  • Table 146. Key Technology Milestones for Future 3D-CPO              271
  • Table 147. Performance Trajectory for Future 3D-CPO      272
  • Table 148. Thermal Management Evolution for 3D-CPO   272
  • Table 149.3D-CPO Vision: NVIDIA Architecture Example 273
  • Table 150. CPO Assembly Process and Bottlenecks            274
  • Table 151. Coupler-FAU Interface Critical Dimensions      275
  • Table 152. Misalignment Loss Characterisation     275
  • Table 153. FAU-PIC Interface Stability Requirements         276
  • Table 154. Grating vs. Edge Coupler Comparison 276
  • Table 155. Grating vs. Edge Coupler Comparison 277
  • Table 156. Optical Alignment Challenges Overview             278
  • Table 157. Active vs. Passive Alignment Comparison         279
  • Table 158. Fiber Attach Methods Comparison        282
  • Table 159. FAU Supplier Landscape               283
  • Table 160. Alignment Structure Benchmark              285
  • Table 161. SENKO Key CPO Solutions           286
  • Table 162. Suppliers of Optical Components in CPO: Comprehensive Overview             287
  • Table 163. Laser Source Supplier Details    291
  • Table 164. On-Chip Laser Integration Approaches               292
  • Table 165. External Laser Configurations for CPO 293
  • Table 166. External Laser Suppliers 295
  • Table 167. Laser Attach Technology Comparison  296
  • Table 168. Comprehensive Laser Integration Benchmark 298
  • Table 169. Global CPO Market Forecast ($ Millions)            299
  • Table 170.Switch CPO Unit Volume Forecast (Thousands of Optical Engines)  301
  • Table 171. Switch CPO Market Forecast by Switch Generation ($M)         301
  • Table 172. CPO Cost Trajectory Projection 302
  • Table 173. XPU Optical I/O Market Forecast              303
  • Table 174. XPU Optical I/O Market Forecast by Platform ($M)       304
  • Table 175. CPO Cost Trajectory Projection 305
  • Table 176. Total Cost of Ownership Comparison (Per 51.2T Switch, 5-Year Lifetime)    306
  • Table 177. North America CPO Market Forecast    307
  • Table 178.Asia-Pacific CPO Market Forecast            308
  • Table 179. Europe CPO Market Forecast     309
  • Table 180. Rest of World CPO Market Forecast       310
  • Table 181. Global CPO Market Summary    310
  • Table 182. CPO Total Addressable Market Quantification 311
  • Table 183.CPO Serviceable Addressable Market    311
  • Table 184. CPO Component Market Forecast ($M)              312
  • Table 185. CPO Market by Optical Engine Generation ($M)             313
  • Table 186. CPO Commercial Milestones and Representative Products by Period            313
  • Table 187. Generation Share Evolution         314
  • Table 188. Manufacturing Yield Improvement Trajectory  315
  • Table 189. CPO Standards Development Timeline               317
  • Table 190. Market Restraints Summary        318
  • Table 191. CPO Adoption Curve by Segment (Penetration of Addressable Market)         321
  • Table 192. CPO Market Share by Participant (2024-2026) 324
  • Table 193. Near-Term Competitive Evolution            325
  • Table 194. Competitive Landscape Evolution Timeline      326
  • Table 195. Vertical Integration Trends by Participant Type                328
  • Table 196. Vertical Integration by Company              329
  • Table 197. Bull Case Market Forecast ($M) 332
  • Table 198. Base Case Market Forecast ($M)             333
  • Table 199. Bear Case Market Forecast ($M)              334
  • Table 200. Scenario Comparison Summary              334
  • Table 201. Global DATACOM Market Size and Growth        336
  • Table 202. DATACOM Market Growth Drivers            337
  • Table 203. Global Hyperscale Data Centre Capacity           339
  • Table 204. Edge Computing Market Growth               341
  • Table 205. DATACOM Technology Trends Summary             342
  • Table 206. Packaging Technology Evolution for DATACOM              343
  • Table 207. UCIe Specifications and Adoption Timeline      344
  • Table 208. Laser Source Technology Trends              345
  • Table 209. Laser Source Comparison for CPO         345
  • Table 210. Scale-Out CPO Market Forecast by Switch Bandwidth ($M)  348
  • Table 211. Scale-Out Technology Enablers by Generation               350
  • Table 212. Scale-Out CPO Competitive Landscape             350
  • Table 213. Scale-Up CPO Market Forecast by Platform ($M)          352
  • Table 214. Scale-Up CPO Market Forecast 352
  • Table 215. Scale-Up CPO Market Evolution Phases             353
  • Table 216. Scale-Up CPO Platform Comparison    353
  • Table 217. Scale-Up vs. Scale-Out CPO Comparison         355
  • Table 218. Scale-Up CPO Competitive Landscape               355
  • Table 219. CPO vs. High-Density Connector Adoption Scenarios               357
  • Table 220. OIF High-Density Connector Specifications (Proposed)           358
  • Table 221. Technology Comparison: CPO vs. High-Density Connector-Enabled Alternatives   358
  • Table 222. Scenario Impact by Market Segment     359
  • Table 223. High-Density Connector Development Roadmap vs. CPO Timeline 360
  • Table 224. Why High-Density Connectors Are Unlikely to Derail CPO      360
  • Table 225. Scenario Summary and Strategic Implications               361
  • Table 226. NVIDIA CPO Supply Chain Geographic Distribution    361
  • Table 227. Taiwan IC Industry Market Share Evolution (2021-2025)          362
  • Table 228. TSMC COUPE Platform Technical Specifications           364
  • Table 229. External Laser Source Suppliers for NVIDIA CPO          365

 

List of Figures

  • Figure 1. Anatomy of a Modern AI Data Centre         39
  • Figure 2. Network Switch Architecture in Data Centres     40
  • Figure 3. Switch IC Bandwidth Evolution Timeline (2015-2036)   43
  • Figure 4. Optical Transceiver Technology Migration Path (Pluggable → Near-Package → CPO)  46
  • Figure 5. Optical Engine Component Architecture                50
  • Figure 6. Co-Packaged Optics 1.0: Typical Integration Flow.          51
  • Figure 7. Heterogeneous Integration Concept Diagram    52
  • Figure 8. Evolution from 2D to 2.5D to 3D Integration          60
  • Figure 9. Integration Technology Progression Roadmap    60
  • Figure 10. Switch ASIC with pluggable optics versus co-packaged optics            79
  • Figure 11. LLM Parameter Growth Timeline (GPT-1 to GPT-5 and Beyond)             89
  • Figure 12. DGX H100/H200system topology             92
  • Figure 13. NVIDIA Rubin Architecture Overview      93
  • Figure 14. Scale-Up Network Topology (NVLink, NVSwitch)            95
  • Figure 15. Scale-Out and Scale-Up Network Topology (Ethernet/InfiniBand)      97
  • Figure 16. Three-Tier Network Architecture Diagram           98
  • Figure 17. Interconnect Technology Roadmap (2020-2036)           100
  • Figure 18. On-Board Optics Configuration 104
  • Figure 19. Switch ASIC Bandwidth Scaling (51.2T → 102.4T → 204.8T)     109
  • Figure 20. Copper-to-Optical Migration Roadmap 116
  • Figure 21. Current AI System Interconnect Architecture    117
  • Figure 22. AI Architecture Evolution (2026-2030)  123
  • Figure 23. AI Architecture Vision (2031-2036)          125
  • Figure 24. PIC Architecture for CPO Applications  131
  • Figure 25. CPO Key Concepts Illustration   137
  • Figure 26. Power Consumption Comparison (pJ/bit Roadmap)   142
  • Figure 27. Optical I/O Packaging for XPUs  158
  • Figure 28. Schematic view of three optically enabled data center platforms (LightningValley2, ThunderValley and Pegasus) and the Aurora test and measurement platform contained within the Nexus rack, which allows intra-rack and inter-rack connectivity betwee                162
  • Figure 29. Semiconductor Packaging Evolution Timeline 166
  • Figure 30. 2.5D Packaging Structure Diagram          177
  • Figure 31. 2.5D Si-Based Packaging Roadmap       189
  • Figure 32. EMIB implementation (silicon bridge).  191
  • Figure 33. FPGA + HBM in 2.5D package with interposer. 191
  • Figure 34. RDL Fabrication Process Flow    194
  • Figure 35. Panel-Level Fan-Out Process      197
  • Figure 36. Wafer-Level Fan-Out Process      198
  • Figure 37. Glass Core Interposer Structure                207
  • Figure 38. Glass Interposer Manufacturing Process Flow 211
  • Figure 39. (a) Switch composed of 2.5D advanced packaging; (b) TMV-based, (c) TSV-based, and (d) TGV-based advanced packaging architectures.      244
  • Figure 40. ASE Fan-Out CPO Solution           251
  • Figure 41. ASE FOPOP Process Flow              252
  • Figure 42. SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO 255
  • Figure 43. FOEB Integration Process Flow  256
  • Figure 44. TSMC Optical Engine Roadmap 264
  • Figure 45. TSMC iOIS Architecture   265
  • Figure 46. (a) TSMC-SoIC face-to-face (F”F) technology for EIC and PIC bonding. (b) COUPE critical components consist of TSMC-SoIC bond, TDC, embedded micro-lens and metal reflector.   266
  • Figure 47. Bond Pitch Scaling Roadmap      266
  • Figure 48.Scale-Up Optical I/O Technology Roadmap       355

 

 

 

 

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The Global Co-Packaged Optics Market 2026-2036
The Global Co-Packaged Optics Market 2026-2036
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