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The Global Co-Packaged Optics Market 2027-2037

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  • Published: June 2026
  • Pages: 470
  • Tables: 240
  • Figures: 50

 

Co-packaged optics (CPO) represents the most fundamental rethinking of optical interconnect in decades, moving the optical engine from the switch faceplate to a position immediately adjacent to the switch or accelerator silicon. By collapsing the high-speed electrical path from centimetres to millimetres, CPO overcomes the "interconnect wall" — the widening gap between AI bandwidth demand, which doubles roughly every two years at the switch and far faster for model parameters, and per-lane optical speed, which doubles only about every four years. The technology delivers materially better power efficiency and substantially lower latency than pluggable transceivers, addressing the binding power, density and cost-per-bit constraints of AI data centres.

The market divides into scale-out CPO (network-switch optical engines) and scale-up CPO (GPU and AI-accelerator optical I/O), with scale-up overtaking scale-out toward the end of the decade and becoming the dominant segment thereafter. Adoption begins in the highest-bandwidth network switches, where pluggable modules hit physical and economic limits, and extends into AI-accelerator optical I/O as next-generation GPU platforms ramp.

Recent developments have been decisive. NVIDIA committed to the laser supply chain with major strategic investments in Coherent and Lumentum, and moved its Quantum-X and Spectrum-X Photonics CPO switches toward production. TSMC firmed its COUPE roadmap — a 200 Gbps micro-ring modulator in production in 2026, targeting 4 Tbps/mm bandwidth density by 2030 — while GlobalFoundries launched the OCI-MSA-aligned SCALE platform with 8λ and 16λ demonstrated. Ayar Labs joined NVIDIA's NVLink Fusion ecosystem after a Series E raise; Marvell completed its Celestial AI acquisition; and Fabrinet invested in Raytek Semiconductor. The OCI-MSA (AMD, Broadcom, Meta, Microsoft, NVIDIA, OpenAI) emerged as the de facto scale-up interconnect standard.

Counterbalancing the momentum, large-scale NVIDIA CPO production could slip to 2028–2029 on systems-engineering grounds — serviceability, reliability and manufacturing-test yield — elevating near-package optics (NPO) as a pragmatic intermediate and triggering a sharp sell-off across optical equities. Test and manufacturing scale-up, from roughly one million to tens of millions of units annually, is now seen as the binding constraint, demanding automated, dual-domain electrical-and-optical test cells and standardised optical connectors. The consensus is that CPO's direction is settled; its rate of adoption is the central variable, shaped by yield maturation, field reliability and the pace at which hyperscaler qualification converts into volume deployment across scale-up and scale-out networks.

The Global Co-Packaged Optics Market 2027-2037 is a comprehensive market and technology assessment of co-packaged optics across AI data-centre, hyperscale and high-performance-computing applications. As copper and pluggable optics reach fundamental physical and economic limits, CPO is emerging as the foundational interconnect technology for scale-up and scale-out AI networks. This report provides the data, technology analysis and competitive intelligence needed to navigate the transition.

The report assesses the market from 2026 through 2037, segmented by application (switch CPO and XPU optical I/O), by switch bandwidth generation (51.2T, 102.4T, 204.8T+), by integration technology (2D, 2.5D silicon/organic/glass, 3D micro-bump and hybrid bonding), by component, and by region (North America, Asia-Pacific, Europe, Rest of World). It includes bull, base and bear scenarios with probability assessments, unit-volume and pricing trajectories, cost-parity analysis versus pluggables, and total-cost-of-ownership modelling.

Technically, the report covers photonic integrated circuits and silicon photonics; optical-engine architecture; the benefits of CPO in latency, power and data rate; the 200G-per-lane transition; modulator materials (silicon micro-ring, TFLN, BTO, indium phosphide); wavelength-division multiplexing and the "beachfront" fibre-count constraint; channel-count scaling; the end-to-end optical link budget; advanced packaging (silicon, organic and glass interposers, TSV, hybrid bonding); EIC/PIC integration; laser sources and external-laser architectures; fibre array units and detachable connectors; standards (OIF, OCI-MSA, UCIe, XPO, Open CPX); and CPO test and manufacturing scale-up. It also analyses the full industrial ecosystem and supply chain, including recent consolidation and NVIDIA's supply-chain investments.

Report contents include: 

  • Executive summary, key findings, market drivers and restraints, and 2026 recent developments
  • Modern AI data-centre architecture, switch ASIC and SerDes evolution, and the interconnect wall
  • Challenges and solutions for future AI systems
  • Introduction to CPO: PICs, optical engines, three core concepts, benefits, future challenges, and standards
  • Packaging for CPO: 2.5D silicon/organic/glass, 3D bumping and hybrid bonding, EIC/PIC integration options
  • CPO market analysis: definitions, sizing, switch and XPU segments, pricing, regional dynamics, TAM, adoption curves, competitive landscape and scenario analysis
  • Global market trends in DATACOM, hyperscale and edge, plus technology trends (packaging, UCIe, lasers)
  • Market outlook: hybrid pluggable-to-CPO transition, scale-out and scale-up roadmaps, high-density connectors, supply-chain dynamics
  • Company profiles including Advantest, Alphawave Semi, AMD, Amkor Technology, ASE Technology Holdings, Astera Labs, Avicena, AXT, Ayar Labs, Broadcom, CEA-Leti, Celestial AI, Cisco, Coherent, Corning, Credo, DenseLight, EFFECT Photonics, EVG, Fabrinet, FOCI (Fiber Optical Communication Inc.), FormFactor, Foxconn, Furukawa Electric, GlobalFoundries, Henkel, Hewlett Packard Enterprise, Hisense Broadband Multimedia Technologies, IBM Corporation, imec, Intel, JCET Group, Kyocera Corporation, Lightmatter, LightSpeed Photonics, LioniX International, Lumentum and more....

 

 

 

1             EXECUTIVE SUMMARY            37

  • 1.1        Report Overview and Key Findings   37
  • 1.2        Key Developments in 2026   38
  • 1.3        Market Definition and Scope               39
    • 1.3.1    Definition of Co-Packaged Optics (CPO)     39
    • 1.3.2    Scope of This Report 39
  • 1.4        Key Market Drivers and Restraints   39
  • 1.5        Modern High-Performance AI Data Centre Architecture    41
    • 1.5.1    Physical Infrastructure Hierarchy     41
    • 1.5.2    Network Architecture                41
    • 1.5.3    Power and Cooling Considerations 42
  • 1.6        Switches: Key Components in Modern Data Centres          42
    • 1.6.1    Switch Architecture Evolution            43
    • 1.6.2    Switch ASIC Technology         43
    • 1.6.3    Optical Transceiver Requirements   44
  • 1.7        Advancements in Switch IC Bandwidth and the Need for CPO Technology          44
    • 1.7.1    Historical Bandwidth Scaling              45
    • 1.7.2    SerDes Technology Evolution              45
    • 1.7.3    Electrical Signalling Limits    45
    • 1.7.4    Front-Panel Density Constraints      45
    • 1.7.5    Power Consumption Trajectory         46
    • 1.7.6    The Interconnect Wall              46
  • 1.8        Overview of Key Challenges in Data Centre Architectures               46
    • 1.8.1    Thermal Management             47
    • 1.8.2    Power Delivery              47
    • 1.8.3    Cable Management   47
    • 1.8.4    Reliability and Serviceability                47
    • 1.8.5    Standards and Interoperability           47
  • 1.9        Key Trend of Optical Transceivers in High-End Data Centres          48
    • 1.9.1    Historical Evolution   48
    • 1.9.2    Technology Migration Path    48
  • 1.10     Design Decisions: CPO vs. Pluggables Comparison           51
    • 1.10.1 Performance Comparison    51
    • 1.10.2 Operational Comparison       51
    • 1.10.3 Economic Comparison           52
  • 1.11     What is an Optical Engine (OE)?       52
    • 1.11.1 Functional Description            52
    • 1.11.2 Optical Engine Components               52
    • 1.11.3 Performance Parameters       53
  • 1.12     Heterogeneous Integration and Co-Packaged Optics         53
    • 1.12.1 The Heterogeneous Integration Imperative 54
    • 1.12.2 Integration Approaches for CPO       54
    • 1.12.3 TSMC's Role in Heterogeneous Integration 55
  • 1.15     Overview of Interconnection Techniques in Semiconductor Packaging 55
    • 1.15.1 Wire Bonding 56
    • 1.15.2 Flip-Chip Bumping     56
    • 1.15.3 Micro-Bumping            56
    • 1.15.4 Through-Silicon Via (TSV)       56
    • 1.15.5 Hybrid Bonding            57
    • 1.15.6 Redistribution Layer (RDL)    57
  • 1.16     Key CPO Applications: Network Switch and Computing Optical I/O         57
    • 1.16.1 Scale-Out Network Switching            57
    • 1.16.2 Scale-Up Computing Optical I/O      58
  • 1.17     EIC/PIC Integration by Advanced Interconnect Techniques            59
    • 1.17.1 Integration Requirements      59
  • 1.18     2D to 3D EIC/PIC Integration Options            60
    • 1.18.1 2D Integration Architecture   60
    • 1.18.2 2.5D Integration Architecture              61
    • 1.18.3 3D Integration Architecture   62
  • 1.19     Benchmark of Different Packaging Technologies for EIC/PIC         66
  • 1.20     Examples of Packaging a 3D Optical Engine with an IC      67
    • 1.20.1 Configuration 1: EIC-on-PIC with Micro-Bumps     67
    • 1.20.2 Configuration 2: PIC-on-EIC with Through-Silicon Vias     67
    • 1.20.3 Configuration 3: 3D SoIC with Hybrid Bonding        67
  • 1.21     Types of CPO + XPU/Switch ASIC Packaging Structures    68
    • 1.21.1 Type I: Optical Engines on Package Periphery          68
    • 1.21.2 Type II: Optical Engines Co-Located with ASIC on Interposer        68
    • 1.21.3 Type III: 3D Stacked Optical Engines              69
  • 1.22     Challenges and Future Potential of CPO Technology           70
    • 1.22.1 Technical Challenges               70
    • 1.22.2 Commercial Challenges        70
      • 1.22.2.1            Future Potential           70
  • 1.23     NVIDIA vs. Broadcom: Strategic Comparison in AI Infrastructure and CPO         71
    • 1.23.1 NVIDIA's CPO Strategy: Vertical Integration               71
    • 1.23.2 Broadcom's CPO Strategy: Open Ecosystem           72
    • 1.23.3 Competitive Dynamics           72
    • 1.23.4 CPO Product Benchmark: NVIDIA vs. Broadcom   73
    • 1.23.5 NVIDIA and Broadcom: Divergent CPO Ecosystems           74
  • 1.24     Current AI System Architecture          74
    • 1.24.1 NVIDIA DGX/HGX Architecture           74
  • 1.25     Future AI Architecture              75
  • 1.26     Co-packaged optics market map     75
  • 1.27     Market Forecasts        76
    • 1.27.1 Server Boards, CPUs, and GPUs/Accelerators         76
    • 1.27.2 Optical I/O for AI Interconnect CPO Forecast (Units Shipped)      76
    • 1.27.3 Optical I/O for AI Interconnect CPO Forecast (Revenue/Market Size)      77
    • 1.27.4 CPO Network Switches for AI Accelerators Forecast (Units Shipped)      78
    • 1.27.5 CPO Network Switches for AI Accelerators Forecast (Market Size and Revenue)             78
    • 1.27.6 Total CPO Market Overview  79
    • 1.27.7 Total CPO by Different EIC/PIC Integration Technology (Unit Shipments)              80
    • 1.27.8 System Integration of Network Switches by Packaging Technologies       80
    • 1.27.9 System Integration of Optical I/O Forecast by Packaging Technologies  81
  • 1.28     Co-packaged optics (CPO) industrial ecosystem  82
    • 1.28.1 PIC Design Segment  82
    • 1.28.2 ASIC and xPU Design Segment           82
    • 1.28.3 Laser Sources Segment          84
    • 1.28.4 SOI Wafer and Epi-Wafer Segment  84
    • 1.28.5 EIC, Retimers, SerDes, and PHY Segment  85
    • 1.28.6 Connectors and Fibers Segment      86
    • 1.28.7 Foundries Segment    86
    • 1.28.8 Packaging, Assembling, and Testing Segment         87
    • 1.28.9 System and Equipment Segment     88
    • 1.28.10              End Customers (Hyperscalers) Segment    88
    • 1.28.11              Ecosystem Interdependencies and Strategic Implications              89

 

2             CHALLENGES AND SOLUTIONS FOR FUTURE AI SYSTEMS            92

  • 2.1        The Rise and Challenges of Large Language Models (LLMs)           92
    • 2.1.1    The Explosive Growth of AI and Generative AI           92
      • 2.1.1.1 Historical Context and Acceleration               92
      • 2.1.1.2 Compute Demand Scaling   92
      • 2.1.1.3 Generative AI Market Expansion       92
    • 2.1.2    Modern High-Performance AI Data Centre Requirements               94
      • 2.1.2.1 Compute Density Requirements      94
      • 2.1.2.2 Network Topology Requirements      94
      • 2.1.2.3 Availability and Reliability Requirements    94
    • 2.1.3    NVIDIA's State-of-the-Art AI Systems             95
      • 2.1.3.1 DGX H100 and HGX H100     95
    • 2.1.4    Switches: Key Components in Modern Data Centres          97
      • 2.1.4.1 Switch Hierarchy in AI Data Centres               97
  • 2.2        Scale-Up, Scale-Out, and Scale-Across Networks               98
    • 2.2.1    Scale-Up Networks: GPU-to-GPU Interconnects   98
      • 2.2.1.1 NVIDIA NVLink Implementation        98
      • 2.2.1.2 CPO Value Proposition for Scale-Up               99
    • 2.2.2    Scale-Out Networks: Rack-to-Rack Communications      100
      • 2.2.2.1 Ethernet-Based Scale-Out    100
      • 2.2.2.2 InfiniBand for AI            100
      • 2.2.2.3 CPO Value Proposition for Scale-Out            100
    • 2.2.3    Scale-Up, Scale-Out, and Scale-Across Comparison        101
  • 2.3        Challenges in Network Switch Interconnects for High-End Data Centres              102
    • 2.3.1    Roadmap of Interconnect Technology for Network Switches in High-End Data Centres              102
      • 2.3.1.1 Technology Generations         102
    • 2.3.2    SerDes Bottleneck in High-Bandwidth Systems     104
      • 2.3.2.1 SerDes Function          104
      • 2.3.2.2 Channel Loss Challenges      104
    • 2.3.3    Solutions to SerDes Bottlenecks in High-Bandwidth Systems      105
      • 2.3.3.1 Linear-Drive Electronics         105
      • 2.3.3.2 Near-Package Optics                105
      • 2.3.3.3 Co-Packaged Optics 105
    • 2.3.4    Pluggable Optics: Current Bottlenecks and Limitations   106
      • 2.3.4.1 Form Factor Constraints        106
      • 2.3.4.2 Electrical Interface Limitations          106
      • 2.3.4.3 Thermal Management Challenges   106
      • 2.3.4.4 Serviceability Trade-offs        106
    • 2.3.5    On-Board Optics (OBO)          107
    • 2.3.6    Co-Packaged Optics (CPO)  108
      • 2.3.6.1 CPO Architecture        108
      • 2.3.6.2 Key Enabling Technologies    108
      • 2.3.6.3 Performance Benefits              109
      • 2.3.6.4 Implementation Challenges 109
    • 2.3.7    Transmission Losses in Pluggable Optical Transceiver Connections        110
      • 2.3.7.1 Total Path Loss             110
    • 2.3.8    Pluggable Optics vs. CPO      111
    • 2.3.9    Design Decisions for CPO Compared to Pluggables           112
    • 2.3.10 Advancements in Switch IC Bandwidth and the Need for CPO Technology          112
      • 2.3.10.1            Bandwidth Scaling Trajectory              112
      • 2.3.10.2            Physical Constraints at Scale              113
    • 2.3.11 L2 Frontside Network Architecture Diagram: CPO vs. Non-CPO 113
  • 2.4        Challenges in Compute Switch Interconnects (Optical I/O) for High-End Data Centres              115
    • 2.4.1    Number of Copper Wires in Current AI System Interconnects       115
      • 2.4.1.1 NVLink Copper Cable Count               115
      • 2.4.1.2 SuperPOD Cable Complexity              115
    • 2.4.2    Limitations of Current Copper Systems in AI            116
    • 2.4.3    NVIDIA's Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems          118
      • 2.4.3.1 Current Generation: Copper-Centric             118
      • 2.4.3.2 Transition Generation: Hybrid Approach     118
      • 2.4.3.3 Future Generation: Optical-First       118
      • 2.4.3.4 Strategic Implications              118
    • 2.4.4    Copper vs. Optical for High-Bandwidth Systems: Benchmark      118
    • 2.4.5    Migration from Copper to Optical Interconnects for High-End AI Systems            119
    • 2.4.6    Current AI System Architecture          120
    • 2.4.7    L1 Backside Compute Architecture with Copper Systems              121
    • 2.4.8    L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO)    122
    • 2.4.9    Opportunities for Swapping Copper to Optical       122
  • 2.5        Future AI Systems in High-End Data Centres            123
    • 2.5.1    Power Efficiency Comparison: CPO vs. Pluggable Optics vs. Copper Interconnects      123
      • 2.5.1.1 Power Consumption Breakdown      123
    • 2.5.2    Latency of 60cm Data Transmission Technology Benchmark        125
    • 2.5.3    Future AI Architecture (Short to Mid-Term) 125
    • 2.5.4    Future AI Architecture (Long-Term)  127

 

3             INTRODUCTION TO CO-PACKAGED OPTICS (CPO)             130

  • 3.1        Photonic Integrated Circuits (PICs) Key Concepts 130
    • 3.1.1    What are Photonic Integrated Circuits (PICs)?         130
      • 3.1.1.1 Fundamental Definition         130
      • 3.1.1.2 Material Platforms      130
      • 3.1.1.3 Integration Levels        131
    • 3.1.2    PICs vs. Silicon Photonics: What are the Differences?       132
      • 3.1.2.1 Silicon Photonics: A Specific Implementation         132
      • 3.1.2.2 Why Silicon Photonics Dominates CPO       133
    • 3.1.3    PIC Architecture           134
      • 3.1.3.1 Transmit Path Architecture    134
      • 3.1.3.2 Receive Path Architecture     134
      • 3.1.3.3 Supporting Functions               135
    • 3.1.4    Advantages and Challenges of PICs               135
  • 3.2        Optical Engine (OE)   136
    • 3.2.1    What is an Optical Engine?   136
      • 3.2.1.1 Optical Engine Composition               137
      • 3.2.1.2 Optical Engine vs. Pluggable Transceiver    137
    • 3.2.2    How an Optical Engine Works            138
      • 3.2.2.1 Transmit Path Operation         138
      • 3.2.2.2 Receive Path Operation          138
      • 3.2.2.3 Critical Performance Parameters     138
    • 3.2.3    Optical Power Supplies           139
      • 3.2.3.1 Why External Laser Sources?              139
      • 3.2.3.2 External Laser Source Architectures              139
      • 3.2.3.3 Optical Power Delivery            140
  • 3.3        Co-Packaged Optics 140
    • 3.3.1    Three Key Concepts in Co-Packaged Optics (CPO)              140
      • 3.3.1.1 Concept 1: Proximity Integration       140
      • 3.3.1.2 Concept 2: Functional Partitioning 140
      • 3.3.1.3 Concept 3: Coherent Ecosystem Development      141
    • 3.3.2    Key Technology Building Blocks for CPO      142
      • 3.3.2.1 Silicon Photonics PIC               142
      • 3.3.2.2 Electronic IC (EIC)      142
      • 3.3.2.3 EIC-PIC Integration    142
      • 3.3.2.4 Fibre Array Units (FAUs)          142
      • 3.3.2.5 External Laser Source              142
      • 3.3.2.6 Advanced Packaging Platform            143
    • 3.3.3    Benefits of CPO: Latency Reduction              145
      • 3.3.3.1 Sources of Latency in Optical Interconnects            145
      • 3.3.3.2 CPO Latency Advantages      145
    • 3.3.4    Benefits of CPO: Power Consumption Reduction  146
      • 3.3.4.1 Power Consumption Breakdown      146
      • 3.3.4.2 Why CPO Consumes Less Power     146
    • 3.3.5    Benefits of CPO: Data Rate Improvements 147
      • 3.3.5.1 Pluggable Scaling Limitations             147
      • 3.3.5.2 CPO Scaling Advantages       147
      • 3.3.5.3 Data Rate Scaling Roadmap               147
      • 3.3.5.4 The 200G-per-Lane Transition and Silicon Photonics         148
      • 3.3.5.5 Modulator Technology Roadmap and Emerging Materials               148
      • 3.3.5.6 Technology Trends in CPO Driven by Rising Data Rates     148
      • 3.3.5.7 Applicability of Wavelength-Division Multiplexing (WDM)                150
      • 3.3.5.8 Physical Limits on Fibre Count: The Beachfront (Shoreline) Constraint  151
      • 3.3.5.9 Increasing the Number of WDM Channels: Technical Challenges              151
      • 3.3.5.10            The End-to-End Optical Link Budget              152
    • 3.3.6    Overview of Value Proposition of CPO          153
      • 3.3.6.1 Value for Hyperscale Data Centre Operators            153
      • 3.3.6.2 Value for Network Equipment Vendors         153
      • 3.3.6.3 Value for the Technology Ecosystem              153
    • 3.3.7    Future Challenges in CPO     154
      • 3.3.7.1 Manufacturing and Yield Challenges             154
      • 3.3.7.2 Thermal Management Challenges   154
      • 3.3.7.3 Serviceability and Reliability Challenges    154
      • 3.3.7.4 Ecosystem and Standardisation Challenges            154
      • 3.3.7.5 Cost Challenges          155
      • 3.3.7.6 Test and Manufacturing Scale-Up    155
  • 3.4        CPO Standards            156
    • 3.4.1    OIF Co-Packaging Framework            156
    • 3.4.2    OCI-MSA (Optical Compute Interconnect Multi-Source Agreement)        157
    • 3.4.3    OIF Standards for 1.6T and 3.2T CPO Module          157
    • 3.4.4    External Laser Small Form Pluggable (ELSFP) Implementation Agreement          158
    • 3.4.5    Telemetry and Management 158
    • 3.4.6    OIF's CEI-112G XSR / XSR+ PAM4     159
    • 3.4.7    UCIe Standard and Its Relationship to CPO              160
    • 3.4.8    The CPO Standards Process in China           160
    • 3.4.9    XPO and Open CPX Initiatives             161
    • 3.4.10 Near-Package Optics (NPO) as an Intermediate Path         162

 

4             PACKAGING FOR CO-PACKAGED OPTICS (CPO)  163

  • 4.1        Introduction to CPO Packaging         163
    • 4.1.1    Key Components to be Packaged in an Optical Transceiver           163
      • 4.1.1.1 Photonic Integrated Circuit (PIC)      163
      • 4.1.1.2 Electronic Integrated Circuit (EIC)   163
      • 4.1.1.3 Laser Source Interface            163
      • 4.1.1.4 Fibre Array Unit (FAU)               164
      • 4.1.1.5 Host ASIC Interface   164
    • 4.1.2    Heterogeneous Integration and Co-Packaged Photonics 164
      • 4.1.2.1 Why Heterogeneous Integration for CPO?  165
      • 4.1.2.2 Heterogeneous Integration Approaches for CPO   165
      • 4.1.2.3 Integration Hierarchy for CPO             165
    • 4.1.3    CPO for Network Switch: Packaging Concept          165
      • 4.1.3.1 Switch Architecture with CPO            165
      • 4.1.3.2 Package Configuration Options         166
      • 4.1.3.3 Packaging Requirements for Switch CPO    166
    • 4.1.4    1.6 Tbps Co-Packaged Optics for Network Switch                167
      • 4.1.4.1 Integration Approach                167
    • 4.1.5    CPO as Optical I/O for XPUs: Packaging Concept 168
      • 4.1.5.1 The Scale-Up Interconnect Challenge          168
      • 4.1.5.2 XPU-CPO Packaging Concept             168
      • 4.1.5.3 Implementation Approaches              168
      • 4.1.5.4 NVIDIA's Approach to XPU Optical I/O          172
      • 4.1.5.5 Packaging Implications for XPU Optical I/O               172
      • 4.1.5.6 System Architecture Evolution           172
    • 4.1.6    CPO Integration for Compute Silicon             173
      • 4.1.6.1 System Configuration              173
      • 4.1.6.2 Integration Architecture          174
      • 4.1.6.3 Thermal Partitioning 174
      • 4.1.6.4 Enabled Architectures             174
    • 4.1.7    Overview of CPO Packaging Technologies  174
  • 4.2        Overview and Development Roadmap of 2.5D and 3D Advanced Semiconductor Packaging Technologies  177
    • 4.2.1    Evolution Roadmap of Semiconductor Packaging 177
    • 4.2.2    Semiconductor Packaging Overview             178
    • 4.2.3    Key Metrics for Advanced Semiconductor Packaging Performance          181
    • 4.2.4    Overview of Interconnection Techniques in Semiconductor Packaging 185
    • 4.2.5    Overview of 2.5D Packaging Structure          188
    • 4.2.6    2.5D Package Components 188
    • 4.2.7    Benefits for CPO          188
    • 4.2.8    Challenges for CPO   188
  • 4.3        2.5D Silicon-Based Packaging Technologies            189
    • 4.3.1    2.5D Packaging Involving Silicon as Interconnect  189
    • 4.3.2    Silicon Interposer Technology             189
    • 4.3.3    Silicon Bridge Technology      189
    • 4.3.4    CPO Implications        190
    • 4.3.5    Through-Silicon Via (TSV): Current State and Future            194
      • 4.3.5.1 TSV Fabrication Process         194
      • 4.3.5.2 TSV Technology Generations               195
      • 4.3.5.3 TSV Challenges for CPO         195
      • 4.3.5.4 Future TSV Development        196
    • 4.3.6    Development Trends for 2.5D Silicon-Based Packaging   198
      • 4.3.6.1 Interposer Size Scaling            198
      • 4.3.6.2 Routing Density Advancement           198
      • 4.3.6.3 Cost Reduction Initiatives     198
      • 4.3.6.4 Integration with Advanced Features                198
    • 4.3.7    Silicon Interposer vs. Silicon Bridge Benchmark    202
    • 4.3.7.1 Implications for CPO 203
  • 4.4        2.5D Organic-Based Packaging Technologies          204
    • 4.4.1    2.5D Packaging: High-Density Fan-Out (FO) Packaging    204
      • 4.4.1.1 Fan-Out Technology Concept             204
      • 4.4.1.2 High-Density Fan-Out Variants          204
      • 4.4.1.3 Advantages for CPO  204
      • 4.4.1.4 Challenges for CPO   204
    • 4.4.2    Redistribution Layer (RDL)    205
      • 4.4.2.1 RDL Fabrication Process        205
      • 4.4.2.2 RDL Design Considerations for CPO              205
    • 4.4.3    Electronic Interconnects: SiO2 vs. Organic Dielectric         206
    • 4.4.4    Panel Level Fab-Out  208
      • 4.4.4.1 Panel-Level Processing           208
      • 4.4.4.2 Advantages for CPO  208
      • 4.4.4.3 Challenges for CPO   208
    • 4.4.5    Wafer Level Fan-Out 209
      • 4.4.5.1 Wafer-Level Processing          209
      • 4.4.5.2 Advantages for WLFO               209
      • 4.4.5.3 Challenges for WLFO                210
    • 4.4.6    Wafer-Level Fan-Out vs. Panel-Level Fan-Out         210
      • 4.4.6.1 Selection Criteria for CPO     211
    • 4.4.7    Key Trends in Fan-Out Packaging     211
    • 4.4.8    Challenges in Future Fan-Out Processes    213
      • 4.4.8.1 Die Shift and Placement Accuracy   213
      • 4.4.8.2 Warpage Control         213
      • 4.4.8.3 Yield and Cost               213
      • 4.4.8.4 High-Frequency Performance             214
  • 4.5        2.5D Glass-Based Packaging Technologies               216
    • 4.5.1    Roles of Glass in Semiconductor Packaging            216
      • 4.5.1.1 Glass Properties Relevant to Packaging      216
      • 4.5.1.2 Applications in Packaging     217
      • 4.5.1.3 Glass Core as Interposer for Advanced Semiconductor Packaging          218
    • 4.5.2    Overcoming Limitations of Silicon Interposers with Glass              220
      • 4.5.2.1 Size Limitation              220
      • 4.5.2.2 Optical Opacity            220
      • 4.5.2.3 Dielectric Loss              220
      • 4.5.2.4 Cost Structure               220
      • 4.5.2.5 Remaining Silicon Advantages           220
    • 4.5.3    Glass vs. Molding Compound             221
      • 4.5.3.1 Implications for CPO 222
    • 4.5.4    Glass Core (Interposer) Package: Process Flow     222
    • 4.5.5    Challenges of Glass Packaging         224
      • 4.5.5.1 Handling and Breakage           224
      • 4.5.5.2 Via Formation and Metallisation       224
      • 4.5.5.3 Thermal Conductivity               224
      • 4.5.5.4 RDL Adhesion                224
      • 4.5.5.5 Warpage Control         224
  • 4.6        3D Advanced Semiconductor Packaging Technologies     230
    • 4.6.1    Evolution of Bumping Technologies 230
      • 4.6.1.1 Solder Bumps (C4)     230
      • 4.6.1.2 Copper Pillar Bumps 230
      • 4.6.1.3 Micro-Bumps 230
      • 4.6.1.4 Hybrid Bonding (Bumpless) 230
    • 4.6.2    Challenges in Scaling Bumps             230
      • 4.6.2.1 Mechanical Challenges          230
      • 4.6.2.2 Electrical Challenges               231
      • 4.6.2.3 Manufacturing Challenges   231
      • 4.6.2.4 Implications for CPO 231
    • 4.6.3    Micro-Bump for Advanced Semiconductor Packaging      234
      • 4.6.3.1 Micro-Bump Structure             234
    • 4.6.4    Bumpless Cu-Cu Hybrid Bonding    234
      • 4.6.4.1 Hybrid Bonding Concept        234
      • 4.6.4.2 Process Fundamentals           234
      • 4.6.4.3 Key Characteristics   234
      • 4.6.4.4 Benefits for CPO          235
    • 4.6.5    Three Ways of Cu-Cu Hybrid Bonding: Benchmark              235
      • 4.6.5.1 Die-to-Die (D2D)         235
      • 4.6.5.2 Die-to-Wafer (D2W)  235
      • 4.6.5.3 Wafer-to-Wafer (W2W)            235
    • 4.6.6    Challenges in Cu-Cu Hybrid Bonding Manufacturing Process      237
  • 4.7        CPO Packaging: EIC and PIC Integration      241
    • 4.7.1    EIC/PIC Integration by Conventional Interconnect Techniques    241
      • 4.7.1.1 Wire Bond Integration               241
      • 4.7.1.2 Flip-Chip Integration (2D)      242
    • 4.7.2    EIC/PIC Integration by Emerging Interconnect Techniques              244
      • 4.7.2.1 2.5D Interposer Integration   244
      • 4.7.2.2 3D Micro-Bump Stacking       244
      • 4.7.2.3 3D Hybrid Bonding     244
    • 4.7.3    2D to 3D EIC/PIC Integration Options            246
      • 4.7.3.1 Technology Transition Drivers             248
      • 4.7.3.2 2D to 3D Integration Evolution            249
    • 4.7.4    Integration Roadmap by CPO Segment        250
    • 4.7.5    Benchmarking of Different Packaging Technologies for EIC/PIC  251
    • 4.7.6    Pros and Cons of 2D Integration of EIC/PIC               251
    • 4.7.7    Pros and Cons of 2.5D Integration of EIC/PIC           252
    • 4.7.8    Pros and Cons of 3D Hybrid Integration of EIC/PIC               253
    • 4.7.9    Pros and Cons of 3D Monolithic Integration of EIC/PIC      254
  • 4.8        TSV for EIC/PIC Integration   255
    • 4.8.1    TSV for EIC/PIC Integration in CPO  255
      • 4.8.1.1 TSV Configurations for EIC/PIC          255
      • 4.8.1.2 Design Considerations            255
    • 4.8.2    Benefits of TSV for PIC/EIC Integration          256
    • 4.8.3    Cisco Packaging Architectures of Optical Engine Over Generations         257
    • 4.8.4    Cisco: 2.5D Chip-on-Chip (CoC) Packaging Architecture for EIC/PIC Integration            258
      • 4.8.4.1 Architecture Description        258
      • 4.8.4.2 Manufacturing Considerations          258
    • 4.8.5    Cisco: 3D TSV for PIC/EIC Integration            259
      • 4.8.5.1 Architecture Description        259
      • 4.8.5.2 Benefits of TSV Integration    259
      • 4.8.5.3 Manufacturing Considerations          259
    • 4.8.6    Key TSV Fabrication Steps and Challenges in CPO               259
      • 4.8.6.1 Fabrication Process Flow      260
    • 4.8.7    Packaging Options for Silicon Photonics     261
    • 4.8.8    Pros and Cons of 2.5D Si Interposer for EIC/PIC Integration           261
  • 4.9        Fan-Out for EIC/PIC Integration         262
    • 4.9.1    ASE's Proposed Fan-Out Solution for CPO Packaging        262
      • 4.9.1.1 ASE Fan-Out CPO Concept  262
    • 4.9.2    FOPOP from ASE: Process    263
    • 4.9.3    Analysis of FOPOP vs. Wire Bond Packaging for CPO          264
    • 4.9.4    Optical Packaging Process Considerations for Silicon Photonics - ASE  265
    • 4.9.5    SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO        266
    • 4.9.6    Process Flow of Integrating PIC and EIC in a FOEB Structure         267
    • 4.9.7    Process Challenges in Packaging Optical Engines                268
    • 4.9.8    Challenges of Using Fan-Out for EIC/PIC Integration          268
  • 4.10     Glass-Based CPO Packaging Technologies               269
    • 4.10.1 Glass-Based Co-Packaged Optics  269
      • 4.10.1.1            Corning's Glass CPO Vision 269
    • 4.10.2 Glass CPO Package Architecture      270
    • 4.10.3 Glass-Based CPO Process Development    271
      • 4.10.3.1            Corning's 102.4 Tb/s Test Vehicle Demonstration 272
    • 4.10.4 3D Heterogeneous Integration of EIC/PIC on a Glass Interposer 272
      • 4.10.4.1            Architecture Rationale             272
      • 4.10.4.2            Package Architecture                273
      • 4.10.4.3            Process Flow  273
      • 4.10.4.4            Representative Switch Module Example     274
      • 4.10.4.5            Market Trajectory        275
  • 4.11     Hybrid Bonding for EIC/PIC Integration         275
    • 4.11.1 TSMC: Integrated HPC Technology Platform for AI 275
    • 4.11.2 iOIS: Integrated Optical Interconnection System from TSMC        276
    • 4.11.3 Combining EIC and PIC with 3D SoIC Bond               277
    • 4.11.4 Roadmap of Bond Pitch Scaling        278
  • 4.12     System Integration of Optical Engine and ASIC/XPU            279
    • 4.12.1 Co-Packaging vs. Co-Packaged Optics (CPO)         279
    • 4.12.2 Three Types of CPO + XPU/Switch ASIC Packaging Structures      280
      • 4.12.2.1            Type 1: 2D/2.5D Peripheral Integration          280
      • 4.12.2.2            Type 2: 2.5D with Embedded Bridge               280
      • 4.12.2.3            Type 3: 3D Stacked Integration           280
  • 4.13     Future 3D-CPO Structure       281
    • 4.13.1 Future 3D-CPO Architecture Vision 281
    • 4.13.2 NVIDIA's 3D Integration of SoC, HBM, EIC, and PIC on Co-Packaged Substrates             285
      • 4.13.2.1.1        Architecture Overview             285
      • 4.13.2.1.2        Integration Approach                285
      • 4.13.2.1.3        Key Innovations            285
  • 4.14     Optical Alignment and Laser Integration     286
    • 4.14.1 How CPO is Built and the Bottleneck             286
    • 4.14.2 The fibre attach bottleneck   286
    • 4.14.3 Interface Between Coupler and FAU              287
    • 4.14.4 Grating vs. Edge Couplers: Challenges in High-Density Optical I/O for Silicon Photonics          288
    • 4.14.5 Challenges in High-Density Optical I/O for Silicon Photonics       289
  • 4.15     Fiber Array Unit (FAU)               290
    • 4.15.1 Optical Alignment Challenges and Solutions           290
    • 4.15.2 Two Alignment Approaches 291
    • 4.15.3 Reducing Optical Fiber Packaging Complexity        292
    • 4.15.4 Key Technical Challenges      292
      • 4.15.4.1            The Size Mismatch Between Silicon Waveguides and Planar Optical Fibers        292
    • 4.15.5 Fiber Attach Methods               293
    • 4.15.6 Key Players in FAU for CPO   295
    • 4.15.7 Benchmark of Optical Fiber Alignment Structure Variations          295
    • 4.15.8 Suppliers of Other Optical Components in CPO    298
  • 4.16     Suppliers of Other Optical Components in CPO    298
  • 4.17     Laser Integration          303
    • 4.17.1 Laser sources for CPO             303
    • 4.17.2 On-Chip Light Source Integration Methods                304
    • 4.17.3 External Lasers for CPO          304
    • 4.17.4 Laser Attach Technology Benchmark            308
    • 4.17.5 Benchmark of Different Laser Integration Technologies    309

 

5             CO-PACKAGED OPTICS MARKET ANALYSIS               311

  • 5.1        CPO Market Definition and Scope    311
  • 5.2        CPO Market Size and Growth Projections   311
  • 5.3        Switch CPO Market Analysis               312
    • 5.3.1    Market Overview and Drivers               312
    • 5.3.2    Deployment Timeline and Adoption Phases             312
    • 5.3.3    Volume Projections and Market Sizing          312
    • 5.3.4    Market Concentration and Regional Distribution   313
    • 5.3.5    Pricing Trajectory and Cost Dynamics          314
  • 5.4        XPU Optical I/O Market Analysis       314
    • 5.4.1    Market Drivers and Value Proposition           314
    • 5.4.2    Adoption Timeline and Platform Evolution 315
    • 5.4.3    Volume and Revenue Projections     315
    • 5.4.4    Market Segmentation by Platform    316
    • 5.4.5    Technology Requirements and Differentiation         316
  • 5.5        CPO Pricing and Cost Analysis          317
    • 5.5.1    Current Pricing Landscape   317
    • 5.5.2    Cost Trajectory and Reduction Drivers          317
    • 5.5.3    Cost Parity Timeline and Dynamics 318
    • 5.5.4    Pricing Strategy Implications               319
  • 5.6        Regional Market Dynamics   319
    • 5.6.1    North America              320
    • 5.6.2    Asia-Pacific    320
    • 5.6.3    Europe                321
    • 5.6.4    Rest of World 322
  • 5.7        Total Addressable Market Analysis  323
    • 5.7.1    Core TAM Segments  324
    • 5.7.2    Serviceable Addressable Market (SAM)       324
  • 5.8        Market Forecast by Component        325
  • 5.9        Market Forecast by Technology Generation               326
    • 5.9.1    Optical Engine Bandwidth Evolution              326
    • 5.9.2    Generation Lifecycle Analysis            327
  • 5.10     Market Restraints and Barriers           328
    • 5.10.1 Manufacturing Yield and Cost            328
    • 5.10.2 Serviceability and Field Replacement Concerns    329
    • 5.10.3 Standards Maturity and Interoperability       329
    • 5.10.4 Supply Chain Capacity Constraints               330
    • 5.10.5 Competitive Alternatives        331
  • 5.11     Adoption Curve Analysis        332
    • 5.11.1 Technology Adoption Framework     332
      • 5.11.1.1            Innovators (2024-2026)          332
      • 5.11.1.2            Early Adopters (2026-2028) 333
      • 5.11.1.3            Early Majority (2028-2031)   333
      • 5.11.1.4            Late Majority (2031-2034)     334
      • 5.11.1.5            Laggards (2034+)        334
    • 5.11.2 Segment-Specific Adoption Curves                335
  • 5.12     Adoption Accelerators and Inhibitors            335
    • 5.12.1 Adoption Curve Implications               336
  • 5.13     Competitive Landscape Evolution   336
    • 5.13.1 Current Competitive Positioning      336
    • 5.13.2 Integrated Device Manufacturers (IDMs)     336
    • 5.13.3 Silicon Photonics Specialists              337
    • 5.13.4 Foundry/OSAT Providers         337
    • 5.13.5 System Vendors           337
    • 5.13.6 Laser Suppliers             337
    • 5.13.7 Competitive Dynamics and Market Structure Evolution    338
      • 5.13.7.1            Near-Term Dynamics (2025-2028)  338
        • 5.13.7.1.1        Expected Evolution (2028)    338
      • 5.13.7.2            Mid-Term Dynamics (2028-2032)     339
        • 5.13.7.2.1        Expected Evolution (2032)    339
      • 5.13.7.3            Long-Term Dynamics (2032-2036)  339
        • 5.13.7.3.1        Expected Evolution (2036)    340
    • 5.13.8 Vertical Integration Trends    340
      • 5.13.8.1            Integration Strategy Framework         340
        • 5.13.8.1.1        Full Vertical Integration (Broadcom, Intel Model)   340
        • 5.13.8.1.2        Partial Integration (Cisco, NVIDIA Model)    341
        • 5.13.8.1.3        Fabless/Assembly-Light (Ayar Labs, Ranovus Model)         341
        • 5.13.8.1.4        Platform Provider (TSMC Model)       341
      • 5.13.8.2            Strategic Implications of Integration Trends              343
    • 5.13.9 Recent Developments — Q1 2026  343
    • 5.13.10              Recent Developments — Q2 2026  344
  • 5.14     Scenario Analysis       345
    • 5.14.1 Scenario Framework 345
    • 5.14.2 Scenario Definitions 345
    • 5.14.3 Bull Case Scenario     345
    • 5.14.4 Base Case Scenario  346
    • 5.14.5 Bear Case Scenario   346
    • 5.14.6 Optical transceiver market   347
    • 5.14.7 Scenario Comparison and Key Variables    348

 

6             GLOBAL MARKET TRENDS IN DATACOM     349

  • 6.1        Introduction to DATACOM Market Dynamics            349
    • 6.1.1    Overview of the Data Communications Market       349
      • 6.1.1.1 Market Definition and Scope               349
      • 6.1.1.2 Market Size and Growth          349
    • 6.1.2    Key Market Drivers      349
      • 6.1.2.1 Artificial Intelligence and Machine Learning             349
      • 6.1.2.2 Cloud Computing Growth     350
      • 6.1.2.3 Data Growth   350
      • 6.1.2.4 Power and Sustainability Pressures                350
    • 6.1.3    The Optical Transceiver Market Context       351
  • 6.2        Application Trends     351
    • 6.2.1    AI and Machine Learning Workload Growth               351
      • 6.2.1.1 The AI Training Revolution     351
      • 6.2.1.2 Training Cluster Architecture Evolution        351
      • 6.2.1.3 AI Inference Deployment        352
      • 6.2.1.4 Market Quantification              352
      • 6.2.1.5 Implications for CPO 352
    • 6.2.2    Hyperscale Data Centre Expansion 352
      • 6.2.2.1 Defining Hyperscale  353
    • 6.2.3    Global Hyperscale Capacity                353
    • 6.2.4    Regional Distribution                353
    • 6.2.5    Hyperscaler Investment Trends         353
      • 6.2.5.1 Capital expenditure acceleration     353
      • 6.2.5.2 AI-Specific Infrastructure       353
      • 6.2.5.3 Implications for CPO 354
    • 6.2.6    Edge Computing and Distributed AI                354
      • 6.2.6.1 Market Growth              354
    • 6.2.7    Edge AI Applications 354
    • 6.2.8    Edge Network Architecture   354
  • 6.3        Technology Trends      355
    • 6.3.1    Technology Trends Overview               355
      • 6.3.1.1 Key Technology Vectors          355
      • 6.3.1.2 Technology Interdependencies          356
    • 6.3.2    Technology Trends: Packaging           356
    • 6.3.3    Universal Chiplet Interconnect Express (UCIe)       357
    • 6.3.4    Laser Sources for CPO            358
    • 6.3.5    External vs. Integrated Laser                358
    • 6.3.6    Silicon Photonics Share of Datacom              359

 

7             MARKET OUTLOOK    360

  • 7.1        Hybrid Pluggable-to-CPO Transition, 2026–2030  360
  • 7.2        Scale-Out Outlook     361
    • 7.2.1    Scale-Out CPO Market Evolution     361
      • 7.2.1.1 Scale-Out Market Drivers       361
      • 7.2.1.2 Market Evolution Phases        361
      • 7.2.1.3 Scale-Out CPO Market Forecast       361
    • 7.2.2    Scale-Out Technology Roadmap      362
      • 7.2.2.1 Technology Generation Evolution     362
      • 7.2.2.2 Technology Enablers by Generation                363
    • 7.2.3    Scale-Out Key Players and Competitive Landscape            363
  • 7.3        Scale-Up Outlook       364
    • 7.3.1    Scale-Up CPO Market Evolution       364
    • 7.3.2    Copper to Optical Transition               365
    • 7.3.3    Optical I/O Solution   365
    • 7.3.4    Scale-Up CPO Market Forecast         365
    • 7.3.5    Market Evolution Phases        365
    • 7.3.6    Scale-Up Technology Roadmap        367
      • 7.3.6.1 NVIDIA Optical I/O Evolution               367
      • 7.3.6.2 AMD Optical I/O Evolution    367
      • 7.3.6.3 Custom Silicon Optical I/O   368
    • 7.3.7    Scale-Up Key Players and Competitive Landscape              369
      • 7.3.7.1 Competitive Landscape Overview   369
  • 7.4        High-Density Connectors      370
    • 7.4.1    High-Density Connectors vs. CPO   370
      • 7.4.1.1 Scenario 1: Connectors Enable Extended Pluggable (Low CPO Impact) 370
      • 7.4.1.2 Scenario 2: Connectors Complement CPO (Moderate Impact)   370
      • 7.4.1.3 Scenario 3: Connectors Enable "Near-Packaged" Optics (Moderate CPO Impact)         370
      • 7.4.1.4 Scenario 4: Connector Development Delays (Positive CPO Impact)        370
    • 7.4.2    Detachable connectors          375
  • 7.5        Emerging Supply Chain Dynamics   375
    • 7.5.1    Geographic Concentration in CPO Supply Chains                375
    • 7.5.2    Laser and component supply chain               378
  • 7.6        Third-Party Suppliers and Systems Integrators        378
    • 7.6.1    Multi-Tier Supply Chain Architecture              378
      • 7.6.1.1 Tier 1: Silicon Photonics Platform     378
      • 7.6.1.2 Tier 2: CPO Assembly (OSAT)              379
      • 7.6.1.3 Tier 3: Fiber Array Unit (FAU) Suppliers          379
      • 7.6.1.4 Tier 4: External Laser Source (ELS) Suppliers            380
      • 7.6.1.5 Tier 5: Optical Fiber Supply   380
      • 7.6.1.6 Tier 6: Optical Sub-Assembly Integration    380
    • 7.6.2    Strategic Implications for Supply Chain Participants          380

 

8             COMPANY PROFILES                382 (68 company profiles)

 

9             APPENDIX        467

  • 9.1        Research Methodology and Data Sources  467

10          REFERENCES 468

 

List of Tables

  • Table 1. CPO Market Drivers and Restraints Analysis         40
  • Table 2. Key Data Centre Architecture Challenges Summary        44
  • Table 3. Key Data Centre Architecture Challenges Summary.       47
  • Table 4. Form Factor Evolution and Density Comparison 49
  • Table 5. Optical Transceiver Power Consumption by Generation 50
  • Table 6. Technology Migration Decision Framework             51
  • Table 7. CPO vs. Pluggables Decision Matrix             52
  • Table 8. Semiconductor Packaging Interconnection Techniques Overview          57
  • Table 9. CPO Application Segmentation (Scale-Out vs. Scale-Up)             59
  • Table 10. EIC/PIC Integration Methods Comparison           60
  • Table 11. Integration Technology Selection Criteria              64
  • Table 12. Detailed Technical Comparison: 2D vs 2.5D vs 3D         65
  • Table 13. 3D Integration Sub-Categories Comparison       66
  • Table 14. Packaging Technology Benchmark for EIC/PIC Integration        66
  • Table 15. CPO Technology Challenges and Mitigation Strategies 71
  • Table 16. NVIDIA vs. Broadcom Strategic Positioning Comparison           72
  • Table 17. NVIDIA vs. Broadcom CPO Product Specifications Benchmark             73
  • Table 18. Server Boards, CPUs, and GPU/Accelerator Forecast (2026-2036)     76
  • Table 19. Optical I/O for AI Interconnect CPO — Unit Shipment Forecast (2026–2037)               77
  • Table 20. Optical I/O for AI Interconnect CPO — Revenue Forecast ($M) (2026–2037) 77
  • Table 21. CPO Network Switches — Unit Shipment Forecast (2026–2037)          78
  • Table 22. CPO Network Switches — Optical Engine Revenue Forecast ($M) (2026–2037)         79
  • Table 23. Total CPO Market Size and Revenue (2026–2037)           79
  • Table 24. Total CPO by EIC/PIC Integration Technology — Unit Shipments (2026–2037)             80
  • Table 25. Network Switch CPO Adoption by Packaging Technology (2026–2037)            81
  • Table 26. Optical I/O Forecast by Packaging Technology  81
  • Table 27. PIC Design Segment - Key Players and Capabilities       82
  • Table 28. ASIC and xPU Design Segment - Key Players and CPO Integration Strategies                83
  • Table 29. Laser Sources Segment - Key Suppliers and Technologies        84
  • Table 30. SOI Wafer and Epi-Wafer Segment - Substrate Suppliers            85
  • Table 31. EIC, Retimers, SerDes, and PHY Segment - High-Speed Electronics Suppliers           85
  • Table 32. Connectors and Fibers Segment - Optical Infrastructure Suppliers     86
  • Table 33. Foundries Segment - Silicon Photonics and Advanced Packaging Capabilities          87
  • Table 34. Packaging, Assembling, and Testing Segment - OSAT and Test Equipment Providers              87
  • Table 35. System and Equipment Segment - OEMs and ODMs    88
  • Table 36. End Customers (Hyperscalers) Segment - Data Centre Operators and AI Leaders    89
  • Table 37. CPO Industrial Ecosystem Summary - Complete Value Chain Overview         90
  • Table 38. AI Model Parameter and Compute Growth (2018-2030)             93
  • Table 39. Global AI Training Compute Demand Growth     93
  • Table 40. AI Data Centre Requirements by Workload Type               95
  • Table 41. Switch Hierarchy in AI Data Centres          98
  • Table 42. Scale-Up vs. Scale-Out vs. Scale-Across Comparison Matrix 101
  • Table 43. SerDes Bandwidth Limitations and Power Consumption           104
  • Table 44. SerDes Bottleneck Solutions Comparison           105
  • Table 45. Pluggable Optics Architecture and Limitations 106
  • Table 46. Signal Loss Comparison: Pluggable vs. CPO (dB)            110
  • Table 47. Comprehensive Pluggable vs. CPO Comparison             111
  • Table 48. Design Decision Framework for CPO Adoption 112
  • Table 49. L2 Network Architecture Comparison     114
  • Table 50.Copper Wire Count in Current AI Systems             115
  • Table 51. Copper Interconnect Specifications by System 116
  • Table 52. Copper System Limitations Summary     117
  • Table 53. Copper vs. Optical Performance Benchmark     118
  • Table 54. Power Consumption by Interconnect Technology            124
  • Table 55. Power Consumption Component Breakdown: Pluggable vs. CPO (400G)       124
  • Table 56. Latency Benchmark Comparison               125
  • Table 57. PIC Component Overview               131
  • Table 58. PICs vs. Silicon Photonics Comparison 132
  • Table 59. Silicon Photonics vs. Other PIC Platforms: Capability Comparison    133
  • Table 60. PIC Advantages and Challenges Summary          136
  • Table 61. Optical Engine vs. Pluggable Transceiver Comparison 137
  • Table 62. External Laser Source Configurations     139
  • Table 63. CPO Technology Building Blocks 143
  • Table 64. CPO Technology Components and Suppliers     144
  • Table 65. Latency Comparison: Pluggable vs. CPO              145
  • Table 66. Data Rate Scaling: Pluggable vs. CPO      147
  • Table 67. Emerging modulator technologies for CPO and high-speed optics      148
  • Table 68. Data-Rate Scaling Levers, Physical Ceilings, and Industry Responses              149
  • Table 69. WDM Variants for Co-Packaged Optics  150
  • Table 70. Representative Multi-Wavelength Source and Platform Demonstrations (2025–2026)          150
  • Table 71. Shoreline (Beachfront) Bandwidth Density           151
  • Table 72. Challenges of Higher WDM Channel Count and Mitigations    152
  • Table 73. CPO Value Proposition Summary               153
  • Table 74. CPO Technical Challenges and Mitigation Approaches               155
  • Table 75. CPO test scale-up: challenges and mitigations 155
  • Table 76. OIF CPO Standards Development Timeline         156
  • Table 77. OIF CPO Framework Functional Partitioning      157
  • Table 78. OIF CPO Module Specifications by Generation 158
  • Table 79. ELSFP Implementation Agreement Key Specifications 158
  • Table 80. CPO Telemetry and Management Requirements              159
  • Table 81. OIF CEI Specifications for CPO Applications      159
  • Table 82. UCIe Specifications and CPO Relationship         160
  • Table 83. China CPO Standards Landscape              161
  • Table 84. Pluggable vs. co-packaged optics: cost and serviceability        161
  • Table 85. CPO Component Packaging Requirements         164
  • Table 86. Switch CPO Package Specifications (Representative)  166
  • Table 87. 1.6 Tbps Optical Engine Performance      167
  • Table 88. XPU Optical I/O Requirements     169
  • Table 89. Advanced Optical I/O Integration Approaches   170
  • Table 90.Overview of CPO Packaging Technologies             176
  • Table 91. Semiconductor Packaging Technology Landscape         180
  • Table 92. Packaging Technology Comparison for CPO        181
  • Table 93. Advanced Packaging Performance Metrics          182
  • Table 94. Overview of Interconnection Techniques in Semiconductor Packaging            186
  • Table 95.  Interconnection Technique Comparison for CPO           188
  • Table 96. Silicon Interposer vs. Silicon Bridge Comparison            190
  • Table 97. Silicon-Based 2.5D Packaging Options  191
  • Table 98. TSV Specifications by Application              194
  • Table 99. TSV Fabrication Process Steps     194
  • Table 100.TSV Technology Evolution               195
  • Table 101. TSV Challenges for CPO Applications   195
  • Table 102. TSV Technology Evolution.            197
  • Table 103. 2.5D Silicon Packaging Development Trends   198
  • Table 104. Key Development Areas by Technology Node  200
  • Table 105. Interposer Size Evolution for CPO            200
  • Table 106. 2.5D Silicon Packaging Roadmap by Vendor    202
  • Table 107. Roadmap Milestones for CPO Integration          202
  • Table 108. Si Interposer vs. Si Bridge Comparison 202
  • Table 109. RDL Technology Specifications 205
  • Table 110. SiO2 vs. Organic Dielectric Comparison            207
  • Table 111. WLFO vs. PLFO Comparison      210
  • Table 112. Fan-Out Packaging Trends           212
  • Table 113. Fan-Out Process Challenges      214
  • Table 114. Glass Properties vs. Silicon and Organic.           217
  • Table 115. Glass Applications in Semiconductor Packaging         218
  • Table 116. Glass Core Interposer Characteristics 219
  • Table 117. Glass vs. Silicon Interposer Comparison           221
  • Table 118. Glass Interposer Benefits for CPO           221
  • Table 119. Glass vs. Molding Compound Properties            221
  • Table 120. Glass Packaging Challenges and Solutions      226
  • Table 121. Bumping Technology Evolution 230
  • Table 122. Bump Scaling Challenges             232
  • Table 123. Micro-Bump Specifications and Applications 234
  • Table 124. Cu-Cu Hybrid Bonding Methods Comparison 236
  • Table 125. Hybrid Bonding Method Selection for CPO Applications          236
  • Table 126. Hybrid Bonding Manufacturing Challenges       238
  • Table 127. Hybrid Bonding Process Maturity by Pitch          241
  • Table 128. Critical Process Parameters for Hybrid Bonding            241
  • Table 129. Conventional EIC/PIC Integration Methods       242
  • Table 130. Conventional Method Advantages and Limitations Summary              243
  • Table 131. Emerging EIC/PIC Integration Methods 245
  • Table 132. 2D to 3D EIC/PIC Integration Options   247
  • Table 133. Technology Transition Drivers     249
  • Table 134. 2D to 3D Integration Evolution   250
  • Table 135. Integration Roadmap by CPO Segment                250
  • Table 136. EIC/PIC Packaging Technology Benchmark      251
  • Table 137. 2D EIC/PIC Integration Pros and Cons  251
  • Table 138. 2.5D EIC/PIC Integration Pros and Cons             252
  • Table 139. 3D Hybrid EIC/PIC Integration Pros and Cons 253
  • Table 140. 3D Monolithic EIC/PIC Integration Pros and Cons        254
  • Table 141. Benefits of TSV for PIC/EIC Integration 257
  • Table 142. TSV Fabrication Challenges in CPO        260
  • Table 143. Si Photonics Packaging Options Comparison 261
  • Table 144. 2.5D Si Interposer Pros and Cons for EIC/PIC  261
  • Table 145. FOPOP vs. WB Packaging Comparison 264
  • Table 146. Optical Engine Packaging Process Challenges               268
  • Table 147. Fan-Out EIC/PIC Integration Challenges             268
  • Table 148. Bond Pitch Scaling Challenges  279
  • Table 149. Co-Packaging vs. CPO Definition Comparison               279
  • Table 150. Future 3D-CPO Architecture Vision        281
  • Table 151. Architecture Evolution by Component 282
  • Table 152. 3D-CPO Integration Approaches              282
  • Table 153. Future 3D-CPO Packaging Structure Types       283
  • Table 154. Key Technology Milestones for Future 3D-CPO              283
  • Table 155. Performance Trajectory for Future 3D-CPO      284
  • Table 156. Thermal Management Evolution for 3D-CPO   284
  • Table 157.3D-CPO Vision: NVIDIA Architecture Example 285
  • Table 158. CPO Assembly Process and Bottlenecks            286
  • Table 159. Coupler-FAU Interface Critical Dimensions      287
  • Table 160. Misalignment Loss Characterisation     287
  • Table 161. FAU-PIC Interface Stability Requirements         288
  • Table 162. Grating vs. Edge Coupler Comparison 288
  • Table 163. Grating vs. Edge Coupler Comparison 289
  • Table 164. Optical Alignment Challenges Overview             290
  • Table 165. Active vs. Passive Alignment Comparison         291
  • Table 166. Fiber Attach Methods Comparison        294
  • Table 167. FAU Supplier Landscape               295
  • Table 168. Alignment Structure Benchmark              297
  • Table 169. SENKO Key CPO Solutions           298
  • Table 170. Suppliers of Optical Components in CPO: Comprehensive Overview             299
  • Table 171. Laser Source Supplier Details    303
  • Table 172. On-Chip Laser Integration Approaches               304
  • Table 173. External Laser Configurations for CPO 305
  • Table 174. External Laser Suppliers 307
  • Table 175. Laser Attach Technology Comparison  308
  • Table 176. Comprehensive Laser Integration Benchmark 310
  • Table 177. Global CPO Market Forecast ($ Millions)            311
  • Table 178.Switch CPO Unit Volume Forecast (Thousands of Optical Engines)  313
  • Table 179. Switch CPO Market Forecast by Switch Generation ($M)         313
  • Table 180. CPO Cost Trajectory Projection 314
  • Table 181. XPU Optical I/O Market Forecast              315
  • Table 182. XPU Optical I/O Market Forecast by Platform ($M)       316
  • Table 183. CPO Cost Trajectory Projection 317
  • Table 184. CPO vs. Pluggable Cost Comparison (Per 800G Equivalent)  318
  • Table 185. Total Cost of Ownership Comparison (Per 51.2T Switch, 5-Year Lifetime)    319
  • Table 186. North America CPO Market Forecast 2026-2037          320
  • Table 187. Asia-Pacific CPO Market Forecast 2026-2037 321
  • Table 188. Europe CPO Market Forecast 2026-2037           322
  • Table 189. Rest of World CPO Market Forecast 2026-2037            322
  • Table 190. Global CPO Market Summary    323
  • Table 191. CPO Total Addressable Market Quantification 324
  • Table 192.CPO Serviceable Addressable Market    324
  • Table 193. CPO Component Market Forecast ($M)              325
  • Table 194. CPO Market by Optical Engine Generation ($M)             326
  • Table 195. CPO Commercial Milestones and Representative Products by Period            326
  • Table 196. Generation Share Evolution         327
  • Table 197. Manufacturing Yield Improvement Trajectory  328
  • Table 198. CPO Standards Development Timeline               330
  • Table 199. Market Restraints Summary        332
  • Table 200. CPO Adoption Curve by Segment (Penetration of Addressable Market)         335
  • Table 201. CPO Market Share by Participant (2024-2026) 338
  • Table 202. Near-Term Competitive Evolution            339
  • Table 203. Competitive Landscape Evolution Timeline      340
  • Table 204. Vertical Integration Trends by Participant Type                342
  • Table 205. Vertical Integration by Company              342
  • Table 206. Bull Case Market Forecast ($M) 346
  • Table 207. Base Case Market Forecast ($M)             346
  • Table 208. Bear Case Market Forecast ($M)              347
  • Table 209.Global optical transceiver market context (USD billion)            347
  • Table 210. Scenario Comparison Summary              348
  • Table 211. Global DATACOM Market Size and Growth        349
  • Table 212. DATACOM Market Growth Drivers            350
  • Table 213. Global optical transceiver market context (USD billion)           351
  • Table 214. Global Hyperscale Data Centre Capacity           353
  • Table 215. Edge Computing Market Growth               354
  • Table 216. DATACOM Technology Trends Summary             355
  • Table 217. Packaging Technology Evolution for DATACOM              356
  • Table 218. UCIe Specifications and Adoption Timeline      357
  • Table 219. Laser Source Technology Trends              358
  • Table 220. Laser Source Comparison for CPO         358
  • Table 221. Scale-Out CPO Market Forecast by Switch Bandwidth ($M) 2026-2037        362
  • Table 222. Scale-Out Technology Enablers by Generation               363
  • Table 223. Scale-Out CPO Competitive Landscape             363
  • Table 224. Scale-Up CPO Market Forecast by Platform ($M)          365
  • Table 225. Scale-Up CPO Market Forecast 366
  • Table 226. Scale-Up CPO Market Evolution Phases             366
  • Table 227. Scale-Up CPO Platform Comparison    367
  • Table 228. Scale-Up vs. Scale-Out CPO Comparison         369
  • Table 229. Scale-Up CPO Competitive Landscape               369
  • Table 230. CPO vs. High-Density Connector Adoption Scenarios               371
  • Table 231. OIF High-Density Connector Specifications (Proposed)           372
  • Table 232. Technology Comparison: CPO vs. High-Density Connector-Enabled Alternatives   372
  • Table 233. Scenario Impact by Market Segment     373
  • Table 234. High-Density Connector Development Roadmap vs. CPO Timeline 373
  • Table 235. Why High-Density Connectors Are Unlikely to Derail CPO      374
  • Table 236. Scenario Summary and Strategic Implications               374
  • Table 237. NVIDIA CPO Supply Chain Geographic Distribution    376
  • Table 238. Taiwan IC Industry Market Share Evolution (2021-2025)          376
  • Table 239. TSMC COUPE Platform Technical Specifications           378
  • Table 240. External Laser Source Suppliers for NVIDIA CPO          380

 

List of Figures

  • Figure 1. Anatomy of a Modern AI Data Centre         42
  • Figure 2. Network Switch Architecture in Data Centres     43
  • Figure 3. Switch IC Bandwidth Evolution Timeline (2015-2036)   46
  • Figure 4. Optical Transceiver Technology Migration Path (Pluggable → Near-Package → CPO)  49
  • Figure 5. Optical Engine Component Architecture                53
  • Figure 6. Co-Packaged Optics 1.0: Typical Integration Flow.          54
  • Figure 7. Heterogeneous Integration Concept Diagram    55
  • Figure 8. Evolution from 2D to 2.5D to 3D Integration          63
  • Figure 9. Integration Technology Progression Roadmap    64
  • Figure 10. Co-packaged optics market map             76
  • Figure 11. Switch ASIC with pluggable optics versus co-packaged optics            83
  • Figure 12. LLM Parameter Growth Timeline (GPT-1 to GPT-5 and Beyond)             93
  • Figure 13. DGX H100/H200system topology             96
  • Figure 14. NVIDIA Rubin Architecture Overview      97
  • Figure 15. Scale-Up Network Topology (NVLink, NVSwitch)            99
  • Figure 16. Scale-Out and Scale-Up Network Topology (Ethernet/InfiniBand)      101
  • Figure 17. Three-Tier Network Architecture Diagram           102
  • Figure 18. Interconnect Technology Roadmap (2020-2036)           104
  • Figure 19. On-Board Optics Configuration 108
  • Figure 20. Switch ASIC Bandwidth Scaling (51.2T → 102.4T → 204.8T)     113
  • Figure 21. Copper-to-Optical Migration Roadmap 120
  • Figure 22. Current AI System Interconnect Architecture    121
  • Figure 23. AI Architecture Evolution (2026-2030)  127
  • Figure 24. AI Architecture Vision (2031-2036)          129
  • Figure 25. PIC Architecture for CPO Applications  135
  • Figure 26. CPO Key Concepts Illustration   141
  • Figure 27. Power Consumption Comparison (pJ/bit Roadmap)   147
  • Figure 28. Optical I/O Packaging for XPUs  169
  • Figure 29. Schematic view of three optically enabled data center platforms (LightningValley2, ThunderValley and Pegasus) and the Aurora test and measurement platform contained within the Nexus rack, which allows intra-rack and inter-rack connectivity betwee                173
  • Figure 30. Semiconductor Packaging Evolution Timeline 178
  • Figure 31. 2.5D Packaging Structure Diagram          189
  • Figure 32. 2.5D Si-Based Packaging Roadmap       201
  • Figure 33. EMIB implementation (silicon bridge).  203
  • Figure 34. FPGA + HBM in 2.5D package with interposer. 203
  • Figure 35. RDL Fabrication Process Flow    206
  • Figure 36. Panel-Level Fan-Out Process      209
  • Figure 37. Wafer-Level Fan-Out Process      210
  • Figure 38. Glass Core Interposer Structure                219
  • Figure 39. Glass Interposer Manufacturing Process Flow 223
  • Figure 40. (a) Switch composed of 2.5D advanced packaging; (b) TMV-based, (c) TSV-based, and (d) TGV-based advanced packaging architectures.      256
  • Figure 41. ASE Fan-Out CPO Solution           263
  • Figure 42. ASE FOPOP Process Flow              264
  • Figure 43. SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO 267
  • Figure 44. FOEB Integration Process Flow  268
  • Figure 45. TSMC Optical Engine Roadmap 276
  • Figure 46. TSMC iOIS Architecture   277
  • Figure 47. (a) TSMC-SoIC face-to-face (F”F) technology for EIC and PIC bonding. (b) COUPE critical components consist of TSMC-SoIC bond, TDC, embedded micro-lens and metal reflector.   278
  • Figure 48. Bond Pitch Scaling Roadmap      278
  • Figure 49.Scale-Up Optical I/O Technology Roadmap       368
  • Figure 50. A demo compute rack with 100% CPO interconnect    394

 

 

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